SRAM_CTRL/MAIN Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.530s	405.707us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.920s	40.693us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.980s	12.870us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.910s	703.686us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.000s	19.904us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.510s	1.514ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.980s	12.870us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	19.904us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.848m	53.285ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	56.610s	9.087ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.889m	27.191ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.823m	5.760ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.152m	77.946ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.810m	29.074ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	45.500s	11.780ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.710m	6.887ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.650s	695.465us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.485m	65.237ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	8.990s	3.012ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	11.730s	718.746us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.600s	1.588ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.187m	64.359ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.440s	2.094ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.209h	923.461ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	13.283us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.800s	231.668us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.800s	231.668us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.920s	40.693us	1	1	100.00
		sram_ctrl_csr_rw	1.980s	12.870us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	19.904us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	15.259us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.920s	40.693us	1	1	100.00
		sram_ctrl_csr_rw	1.980s	12.870us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	19.904us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	15.259us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.880s	21.675ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
		sram_ctrl_tl_intg_err	2.790s	194.406us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.790s	194.406us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.187m	64.359ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.187m	64.359ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.980s	12.870us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.710m	6.887ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.710m	6.887ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.710m	6.887ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	45.500s	11.780ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.420s	2.675ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.880s	21.675ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.500s	4.383ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.530s	405.707us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.530s	405.707us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.710m	6.887ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	45.500s	11.780ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.530s	405.707us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.650s	20.258us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.480s	1.212ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.42183203609065862863519906583771671489335327768380509738561209664350386890944
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 4382746229 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x76) != exp (0x7e)
        UVM_INFO @ 4382746229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.81854327945232503237084760218251543025352662466604126584120125384547714577825
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2675422263 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2675422263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.113618264963103904320914744965683699175397860687130116847371403971691558592443
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  20258387 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  20258387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---