UART Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.230s	458.309us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.800s	19.638us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.760s	15.080us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.010s	1.525ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.320s	307.452us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.650s	67.329us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.760s	15.080us	1	1	100.00
		uart_csr_aliasing	1.320s	307.452us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	25.780s	81.639ms	1	1	100.00
V2	parity	uart_smoke	2.230s	458.309us	1	1	100.00
		uart_tx_rx	25.780s	81.639ms	1	1	100.00
V2	parity_error	uart_intr	21.920s	25.151ms	1	1	100.00
		uart_rx_parity_err	50.450s	54.991ms	1	1	100.00
V2	watermark	uart_tx_rx	25.780s	81.639ms	1	1	100.00
		uart_intr	21.920s	25.151ms	1	1	100.00
V2	fifo_full	uart_fifo_full	21.690s	21.550ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	23.730s	47.990ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.840s	127.137ms	1	1	100.00
V2	rx_frame_err	uart_intr	21.920s	25.151ms	1	1	100.00
V2	rx_break_err	uart_intr	21.920s	25.151ms	1	1	100.00
V2	rx_timeout	uart_intr	21.920s	25.151ms	1	1	100.00
V2	perf	uart_perf	1.497m	23.386ms	1	1	100.00
V2	sys_loopback	uart_loopback	13.530s	5.063ms	1	1	100.00
V2	line_loopback	uart_loopback	13.530s	5.063ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	46.070s	141.273ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.150s	20.221ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.750s	1.158ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	1.970s	1.396ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.451m	128.376ms	1	1	100.00
V2	stress_all	uart_stress_all	8.163m	202.042ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	12.056us	1	1	100.00
V2	intr_test	uart_intr_test	1.740s	14.441us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.290s	58.020us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.290s	58.020us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.800s	19.638us	1	1	100.00
		uart_csr_rw	1.760s	15.080us	1	1	100.00
		uart_csr_aliasing	1.320s	307.452us	1	1	100.00
		uart_same_csr_outstanding	1.380s	95.639us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.800s	19.638us	1	1	100.00
		uart_csr_rw	1.760s	15.080us	1	1	100.00
		uart_csr_aliasing	1.320s	307.452us	1	1	100.00
		uart_same_csr_outstanding	1.380s	95.639us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.740s	121.123us	1	1	100.00
		uart_tl_intg_err	2.280s	182.036us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.280s	182.036us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.177m	3.671ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00