CHIP Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: `91d1222`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	20.810s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	20.810s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.346m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.164m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.121m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.909m	6.661ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.909m	6.661ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.909m	6.661ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	3.006m		0	1	0.00
		chip_sw_example_manufacturer	36.160s		0	1	0.00
		chip_sw_example_concurrency	3.852m	4.896ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.680s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.290s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.710s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.710s		0	1	0.00
V1	xbar_smoke	xbar_smoke	29.650s	53.927us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	12.610s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.399m	8.617ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.452m	4.325ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.044m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.946m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	2.214m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	2.043m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.410s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.410s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.599m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	20.835s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.404m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.404m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.036m	4.282ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.385m	4.000ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.307m	13.844ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.632s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.390s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.076m	27.513ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.913m	6.307ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.502m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.502m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.153s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.082s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.082s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	29.460s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.414m	3.222ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.226m	5.222ms	1	1	100.00
		chip_sw_aes_idle	3.430m	3.215ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.225m	5.483ms	1	1	100.00
		chip_sw_kmac_idle	4.896m	5.029ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.467s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.359s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.561s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.431s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.317s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.469s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.104s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.017s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.322s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.317s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.469s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.104s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.017s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.322s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.113s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.680s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.380s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.910s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.754s		0	1	0.00
		chip_sw_clkmgr_jitter	4.253m	5.715ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.492m	4.915ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.633s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.780s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	49.010s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.240s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	46.870s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	47.180s	10.380us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.054s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.051s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.497s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.620s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.937m	14.524ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	20.082s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	19.961s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.937m	14.524ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	25.239s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.734s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	19.112s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.739s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.273s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.307m	13.844ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.129m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.075m	8.802ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.815m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.181m	4.935ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.653s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.848s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.097s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.815m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.508s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.809s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.164s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.476s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.825s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.938s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.848s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	50.881s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.244m	7.549ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	44.001s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.809s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	56.645s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	21.514s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.712m	10.132ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.141m	14.250ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.129s		0	1	0.00
		chip_prim_tl_access	8.988m	14.726ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.317s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.469s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.104s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.017s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.322s		0	1	0.00
		chip_rv_dm_lc_disabled	12.076m	27.513ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.931m	3.466ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	45.680s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.033m	3.935ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.430m	3.215ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.088m	5.179ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.225m	5.483ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.699m	3.201ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.435m	4.302ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	52.910s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.712m	10.132ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	41.980s	10.180us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.648m	4.340ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.896m	5.029ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.302s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.302s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.166s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.368m	5.525ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.650s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.712m	10.132ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.380s	10.380us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.345s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.113s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.226m	5.222ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.226m	5.222ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.226m	5.222ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.746m	6.144ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.141m	14.250ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.141m	14.250ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.117m	7.035ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.754s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.129s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.404m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.746m	6.144ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.712m	10.132ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.117m	7.035ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.570m	3.499ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.746m	6.144ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.712m	10.132ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.117m	7.035ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.570m	3.499ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.999s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	50.881s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	44.001s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.809s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	56.645s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	21.514s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.827s		0	1	0.00
		chip_prim_tl_access	8.988m	14.726ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.988m	14.726ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.689s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.231s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.051s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.113s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.680s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.380s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.910s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.754s		0	1	0.00
		chip_sw_clkmgr_jitter	4.253m	5.715ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.500m	9.117ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.500m	9.117ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.753m	4.332ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.750m	5.265ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.349m	5.082ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.505m	5.192ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.096m	4.554ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.461m	4.942ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.570m	3.499ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.129m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.129m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.788m	5.167ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.678m	5.002ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.914m	5.521ms	1	1	100.00
		chip_sw_csrng_smoketest	3.034m	5.222ms	1	1	100.00
		chip_sw_gpio_smoketest	3.269m	4.263ms	1	1	100.00
		chip_sw_hmac_smoketest	3.511m	4.426ms	1	1	100.00
		chip_sw_kmac_smoketest	3.538m	4.488ms	1	1	100.00
		chip_sw_otbn_smoketest	4.413m	4.522ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.359m	5.567ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.864m	3.654ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.993m	4.958ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.222m	3.277ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.431m	4.070ms	1	1	100.00
		chip_sw_uart_smoketest	3.366m	5.137ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	37.938s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.680s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	12.610s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.652s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.270m	5.109ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.212m	4.291ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.383m	5.848ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.954m	3.608ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.756s		0	1	0.00
		chip_rv_dm_lc_disabled	12.076m	27.513ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	34.507s		0	1	0.00
		chip_sw_lc_walkthrough_prod	48.299s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	39.051s		0	1	0.00
		chip_sw_lc_walkthrough_rma	46.227s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.756s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.052s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	35.344s		0	1	0.00
		rom_volatile_raw_unlock	10.616s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.898s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.267m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.306m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.449m	4.836ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.449m	4.836ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.710s		0	1	0.00
		chip_same_csr_outstanding	12.340s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.710s		0	1	0.00
		chip_same_csr_outstanding	12.340s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.054m	312.454us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.680s	12.646us	1	1	100.00
		xbar_smoke_large_delays	4.469m	2.440ms	1	1	100.00
		xbar_smoke_slow_rsp	5.162m	2.059ms	1	1	100.00
		xbar_random_zero_delays	1.326m	73.454us	1	1	100.00
		xbar_random_large_delays	16.201m	8.437ms	1	1	100.00
		xbar_random_slow_rsp	7.860m	2.935ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.154m	140.192us	1	1	100.00
		xbar_error_and_unmapped_addr	1.319m	169.216us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	22.610s	15.482us	1	1	100.00
		xbar_error_and_unmapped_addr	1.319m	169.216us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.045m	317.698us	1	1	100.00
		xbar_access_same_device_slow_rsp	22.913m	8.517ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	45.360s	47.767us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.184m	555.166us	1	1	100.00
		xbar_stress_all_with_error	2.940m	207.533us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	30.671m	1.265ms	1	1	100.00
		xbar_stress_all_with_reset_error	54.850s	9.021us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.367s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.474s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.162s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.825s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.466s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.778s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.329s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.354s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.123s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.587s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.999s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.703s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.813s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.426s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.891s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.067s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	10.723s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.213s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	10.952s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.261s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.666s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.349s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.559s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.491s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.614s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.650s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.411s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.855s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.393s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.418s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.891s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.381s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.556s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.002s		0	1	0.00
		rom_e2e_asm_init_dev	11.669s		0	1	0.00
		rom_e2e_asm_init_prod	11.008s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.398s		0	1	0.00
		rom_e2e_asm_init_rma	11.466s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.501s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.391s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.314s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.136s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.225m	4.363ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.211m	3.672ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.659s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.777s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.875s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.056s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.293m	14.784ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	28.979s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.461m	12.256ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.272s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.419s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.659s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.777s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.875s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.759s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.839s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.042s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.192m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.581m	13.337ms	1	1	100.00
		chip_plic_all_irqs_0	9.048m	5.657ms	1	1	100.00
		chip_plic_all_irqs_10	10.027m	6.736ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.233m	5.867ms	1	1	100.00
		chip_sw_dma_abort	3.996m	3.593ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.551s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.118s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.593s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.846s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.603s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.227s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.278s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.820s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.693s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.515s		0	1	0.00
		chip_sw_mbx_smoketest	4.095m	3.995ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.93750340886285413792995247586424318051798824257559293426445983627612003306054
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (897dea)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (bd26c4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 152.993s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.3756561519094172160759813853842944815613242805355392060826660658237840089518
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (543928)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.327s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.60859951341539260967732115942531425887288460949825472428083989059243707985564
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (59b970)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.785s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.102676878447230489060003164073631863737009370316458010379479653351557421269283
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (56a9b0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 145.233s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.28794979354930857960988200312052064580741423027903283993717722730597983041165
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (d57753)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 10.568s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.15785818658520455646965502581465093552637743962221770219975445680334653439254
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.31694586801420635386895415302899354849152765893820136966497887643296510928373
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.93433748334879310864345905076006878499651313049171768864892204404704844595880
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.35150853066199328583508858434665306861298451373826579211362480103085572234683
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.57745145041415414917374055280153768508233116774485847253630320744845124510385
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.64874522117741284673599689992854733793918971648019177812467304544277904544635
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.99882046391553775201902037531743344177729276347683005302642879833401908193877
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.114735036302865932847422915418163331832928520745121362318252695237843640530430
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.77059879345118828706227225888001109907006993370570283224036141603698029608256
Line 487, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30016.798211 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30016.798211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.50765738288965550992156228601462779302940059963462157601070424870248300389341
Line 524, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.500967 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.500967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.36236013152360910926165469462792321268701939633046368225569055701405806376533
Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18021.624194 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18021.624194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.18662098269964521902810036583248939005429251429359142988998142017140849988865
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10132.346236 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (44516681784859144777166033358795878214289706614536351457091936015517400295757 [0x626b8c8ad88fada8b4a0c6d4c7012b93fd7ab735ad1f8a0da7e2700d4e11e94d] vs 28158060873311840154744502848320096446672453852375786252547148852200309588404 [0x3e40e5cdd3c2ca590b2c35f0606f0b7dad990a7e704750a842b4f50e95a901b4])
  UVM_INFO @ 10132.346236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.83051993680718014236866320725313028016777807892575619418893604808186502060182
Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7548.765368 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (107050252812118248137864342013899873450751514959907620056149224761662195557914 [0xecac4bc1a22ea6a28a5d52f49998bab9df1ec5a3a137f1bb43aea0393e7ee61a] vs 44297062077433787070291546383390596695606167616997990635388591990426153868201 [0x61ef3fa726665a27c32a2d37302e1d9013fbfaf7689231b41942d6f905c55ba9])
  UVM_INFO @ 7548.765368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.95141859061590948184403316848034872932629523727299430737119758750891608239969
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4282.362900 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h57a2063d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h0  a_user: 'h2696f  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4282.362900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.25839053899125743945694223912640071478501536256671716405621361228683946844426
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3999.515730 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h585ce0a2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h1  a_user: 'h248f2  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3999.515730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.82743344457479129029687641634283041363434947034063319549954890824314481152453
    Line 495, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4325.402620 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4325.402620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.81372965721396218186818272010479261269580775566082395912666079114070918335046
    Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4331.717500 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4331.717500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.53707943906325553238365610078848617903257900239586332925500948418336766940000
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5191.736480 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5191.736480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.46361206565888649186837246875838774334803984322701097393755443295780775161709
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35874) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.93695044352985354067313284151081595961069791219863149619915815731957475739555
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4835.523928 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35874) { a_addr: 'h1465413  a_data: 'h18eca82e  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'hcf  a_opcode: 'h4  a_user: 'h27f62  d_param: 'h0  d_source: 'hcf  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4835.523928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.60216182294843493118952277918556131277337825389048300363475267080850887012189
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13843.628872 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13843.628872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.11152228669991004427172769309399567337159738382421155997082363627092989312545
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.38205428149786860078357083048791628273678170926790927188784566909081291368149
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3593.443502 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3593.443502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```