AES/MASKED Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	63.863us	1	1	100.00
V1	smoke	aes_smoke	6.000s	88.293us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	55.663us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	77.678us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	122.515us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	142.043us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	110.441us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	77.678us	1	1	100.00
		aes_csr_aliasing	5.000s	142.043us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	6.000s	88.293us	1	1	100.00
		aes_config_error	5.000s	68.400us	1	1	100.00
		aes_stress	5.000s	73.198us	1	1	100.00
V2	key_length	aes_smoke	6.000s	88.293us	1	1	100.00
		aes_config_error	5.000s	68.400us	1	1	100.00
		aes_stress	5.000s	73.198us	1	1	100.00
V2	back2back	aes_stress	5.000s	73.198us	1	1	100.00
		aes_b2b	43.000s	924.263us	1	1	100.00
V2	backpressure	aes_stress	5.000s	73.198us	1	1	100.00
V2	multi_message	aes_smoke	6.000s	88.293us	1	1	100.00
		aes_config_error	5.000s	68.400us	1	1	100.00
		aes_stress	5.000s	73.198us	1	1	100.00
		aes_alert_reset	8.000s	435.441us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	70.078us	1	1	100.00
		aes_config_error	5.000s	68.400us	1	1	100.00
		aes_alert_reset	8.000s	435.441us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	85.406us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	838.919us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	435.441us	1	1	100.00
V2	stress	aes_stress	5.000s	73.198us	1	1	100.00
V2	sideload	aes_stress	5.000s	73.198us	1	1	100.00
		aes_sideload	7.000s	96.501us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	83.546us	1	1	100.00
V2	stress_all	aes_stress_all	17.000s	1.185ms	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	212.692us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	783.085us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	783.085us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	55.663us	1	1	100.00
		aes_csr_rw	5.000s	77.678us	1	1	100.00
		aes_csr_aliasing	5.000s	142.043us	1	1	100.00
		aes_same_csr_outstanding	4.000s	134.218us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	55.663us	1	1	100.00
		aes_csr_rw	5.000s	77.678us	1	1	100.00
		aes_csr_aliasing	5.000s	142.043us	1	1	100.00
		aes_same_csr_outstanding	4.000s	134.218us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	369.138us	1	1	100.00
V2S	fault_inject	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	121.443us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.010ms	1	1	100.00
		aes_tl_intg_err	5.000s	456.562us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	456.562us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	435.441us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	88.293us	1	1	100.00
		aes_stress	5.000s	73.198us	1	1	100.00
		aes_alert_reset	8.000s	435.441us	1	1	100.00
		aes_core_fi	5.000s	199.472us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	150.245us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	66.630us	1	1	100.00
		aes_stress	5.000s	73.198us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	73.198us	1	1	100.00
		aes_sideload	7.000s	96.501us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	66.630us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	66.630us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	66.630us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	66.630us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	66.630us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	73.198us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	73.198us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	129.983us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	129.983us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	73.688us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	129.983us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	435.441us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_ctr_fi	5.000s	51.942us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	129.983us	1	1	100.00
		aes_control_fi	5.000s	48.666us	1	1	100.00
		aes_cipher_fi	5.000s	73.688us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.000s	478.265us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.77382722804990012478118895373049142005095476415421200311975155706558662557918
      Line 166, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 478265005 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 478265005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---