DMA Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.261ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	389.414us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	306.292us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	30.609us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	31.778us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	648.948us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	12.000s	2.223ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	25.896us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	31.778us	1	1	100.00
		dma_csr_aliasing	12.000s	2.223ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.817m	135.052ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	7.200m	74.705ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.850m	18.800ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	38.367m	521.451ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	7.200m	74.705ms	1	1	100.00
V2	dma_abort	dma_abort	6.000s	283.423us	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.450m	25.402ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	22.407us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	464.255us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	464.255us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	30.609us	1	1	100.00
		dma_csr_rw	4.000s	31.778us	1	1	100.00
		dma_csr_aliasing	12.000s	2.223ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	102.611us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	30.609us	1	1	100.00
		dma_csr_rw	4.000s	31.778us	1	1	100.00
		dma_csr_aliasing	12.000s	2.223ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	102.611us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	15.000s	486.438us	1	1	100.00
		dma_generic_stress	38.367m	521.451ms	1	1	100.00
		dma_handshake_stress	7.200m	74.705ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	249.094us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.383m	36.497ms	1	1	100.00
		dma_longer_transfer	5.000s	78.307us	1	1	100.00
		TOTAL			21	21	100.00