EDN Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.770s	145.135us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.690s	21.096us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.860s	15.098us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.360s	173.683us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.210s	40.072us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.050s	77.610us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.860s	15.098us	1	1	100.00
		edn_csr_aliasing	2.210s	40.072us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.050s	48.808us	1	1	100.00
V2	csrng_commands	edn_genbits	2.050s	48.808us	1	1	100.00
V2	genbits	edn_genbits	2.050s	48.808us	1	1	100.00
V2	interrupts	edn_intr	1.660s	34.393us	1	1	100.00
V2	alerts	edn_alert	1.720s	74.001us	1	1	100.00
V2	errs	edn_err	1.780s	21.954us	1	1	100.00
V2	disable	edn_disable	1.700s	16.337us	1	1	100.00
		edn_disable_auto_req_mode	1.830s	190.128us	1	1	100.00
V2	stress_all	edn_stress_all	6.720s	396.479us	1	1	100.00
V2	intr_test	edn_intr_test	1.690s	50.040us	1	1	100.00
V2	alert_test	edn_alert_test	1.850s	59.191us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.910s	46.956us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.910s	46.956us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.690s	21.096us	1	1	100.00
		edn_csr_rw	1.860s	15.098us	1	1	100.00
		edn_csr_aliasing	2.210s	40.072us	1	1	100.00
		edn_same_csr_outstanding	1.800s	148.641us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.690s	21.096us	1	1	100.00
		edn_csr_rw	1.860s	15.098us	1	1	100.00
		edn_csr_aliasing	2.210s	40.072us	1	1	100.00
		edn_same_csr_outstanding	1.800s	148.641us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.370s	456.002us	1	1	100.00
		edn_tl_intg_err	2.730s	177.543us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.670s	15.761us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.720s	74.001us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.370s	456.002us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.370s	456.002us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.370s	456.002us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.370s	456.002us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.720s	74.001us	1	1	100.00
		edn_sec_cm	4.370s	456.002us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.720s	74.001us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.730s	177.543us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	38.170s	2.271ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00