HMAC Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 12.000s 671.010us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.590s 24.219us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.540s 19.289us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.790s 212.600us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.690s 2.000ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.000s 47.582us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.540s 19.289us 1 1 100.00
hmac_csr_aliasing 6.690s 2.000ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 16.430s 5.323ms 1 1 100.00
V2 back_pressure hmac_back_pressure 24.250s 2.496ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.300s 354.709us 1 1 100.00
hmac_test_sha384_vectors 19.120s 822.878us 1 1 100.00
hmac_test_sha512_vectors 5.854m 29.897ms 1 1 100.00
hmac_test_hmac256_vectors 8.440s 540.117us 1 1 100.00
hmac_test_hmac384_vectors 8.300s 261.421us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.502ms 1 1 100.00
V2 burst_wr hmac_burst_wr 18.540s 1.584ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.537m 8.924ms 1 1 100.00
V2 error hmac_error 1.313m 121.227ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.253m 3.529ms 1 1 100.00
V2 save_and_restore hmac_smoke 12.000s 671.010us 1 1 100.00
hmac_long_msg 16.430s 5.323ms 1 1 100.00
hmac_back_pressure 24.250s 2.496ms 1 1 100.00
hmac_datapath_stress 10.537m 8.924ms 1 1 100.00
hmac_burst_wr 18.540s 1.584ms 1 1 100.00
hmac_stress_all 17.865m 43.102ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 12.000s 671.010us 1 1 100.00
hmac_long_msg 16.430s 5.323ms 1 1 100.00
hmac_back_pressure 24.250s 2.496ms 1 1 100.00
hmac_datapath_stress 10.537m 8.924ms 1 1 100.00
hmac_wipe_secret 1.253m 3.529ms 1 1 100.00
hmac_test_sha256_vectors 8.300s 354.709us 1 1 100.00
hmac_test_sha384_vectors 19.120s 822.878us 1 1 100.00
hmac_test_sha512_vectors 5.854m 29.897ms 1 1 100.00
hmac_test_hmac256_vectors 8.440s 540.117us 1 1 100.00
hmac_test_hmac384_vectors 8.300s 261.421us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.502ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 12.000s 671.010us 1 1 100.00
hmac_long_msg 16.430s 5.323ms 1 1 100.00
hmac_back_pressure 24.250s 2.496ms 1 1 100.00
hmac_datapath_stress 10.537m 8.924ms 1 1 100.00
hmac_burst_wr 18.540s 1.584ms 1 1 100.00
hmac_error 1.313m 121.227ms 1 1 100.00
hmac_wipe_secret 1.253m 3.529ms 1 1 100.00
hmac_test_sha256_vectors 8.300s 354.709us 1 1 100.00
hmac_test_sha384_vectors 19.120s 822.878us 1 1 100.00
hmac_test_sha512_vectors 5.854m 29.897ms 1 1 100.00
hmac_test_hmac256_vectors 8.440s 540.117us 1 1 100.00
hmac_test_hmac384_vectors 8.300s 261.421us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.502ms 1 1 100.00
hmac_stress_all 17.865m 43.102ms 1 1 100.00
V2 stress_all hmac_stress_all 17.865m 43.102ms 1 1 100.00
V2 alert_test hmac_alert_test 1.420s 32.825us 1 1 100.00
V2 intr_test hmac_intr_test 1.540s 14.200us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.000s 26.855us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.000s 26.855us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.590s 24.219us 1 1 100.00
hmac_csr_rw 1.540s 19.289us 1 1 100.00
hmac_csr_aliasing 6.690s 2.000ms 1 1 100.00
hmac_same_csr_outstanding 2.780s 271.599us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.590s 24.219us 1 1 100.00
hmac_csr_rw 1.540s 19.289us 1 1 100.00
hmac_csr_aliasing 6.690s 2.000ms 1 1 100.00
hmac_same_csr_outstanding 2.780s 271.599us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.770s 374.331us 1 1 100.00
hmac_tl_intg_err 3.670s 1.321ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.670s 1.321ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 12.000s 671.010us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.850s 89.865us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 44.770s 25.232ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.510s 136.797us 1 1 100.00
TOTAL 28 28 100.00