I2C Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: `47374bd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	35.260s	1.972ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.180s	1.017ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.690s	29.837us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.810s	85.490us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.050s	676.528us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.330s	151.966us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.150s	67.015us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.810s	85.490us	1	1	100.00
		i2c_csr_aliasing	2.330s	151.966us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.570s	1.059ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.239m	9.010ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	6.542m	47.232ms	1	1	100.00
V2	host_override	i2c_host_override	1.710s	40.398us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	47.560s	23.897ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.692m	2.269ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.840s	76.776us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.060s	302.392us	1	1	100.00
		i2c_host_fifo_reset_rx	10.460s	252.178us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	32.950s	7.847ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	33.150s	2.931ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.900s	187.025us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.850s	5.010ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	49.540s	103.719ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.270s	620.766us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.430s	754.367us	1	1	100.00
		i2c_target_intr_smoke	4.360s	601.582us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.330s	253.118us	1	1	100.00
		i2c_target_fifo_reset_tx	1.870s	866.540us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.294m	44.353ms	1	1	100.00
		i2c_target_stress_rd	9.430s	754.367us	1	1	100.00
		i2c_target_intr_stress_wr	30.350s	10.075ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.390s	5.549ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	11.580s	4.017ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.690s	671.738us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.440s	10.018ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.510s	587.357us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.710s	106.242us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	6.542m	47.232ms	1	1	100.00
		i2c_host_perf_precise	9.100s	582.982us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	33.150s	2.931ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.130s	205.718us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.020s	1.134ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.860s	448.644us	1	1	100.00
		i2c_target_nack_txstretch	2.650s	179.168us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	14.910s	2.080ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.600s	471.133us	1	1	100.00
V2	alert_test	i2c_alert_test	1.460s	121.076us	1	1	100.00
V2	intr_test	i2c_intr_test	1.590s	62.465us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.980s	309.720us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.980s	309.720us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.690s	29.837us	1	1	100.00
		i2c_csr_rw	1.810s	85.490us	1	1	100.00
		i2c_csr_aliasing	2.330s	151.966us	1	1	100.00
		i2c_same_csr_outstanding	2.150s	88.890us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.690s	29.837us	1	1	100.00
		i2c_csr_rw	1.810s	85.490us	1	1	100.00
		i2c_csr_aliasing	2.330s	151.966us	1	1	100.00
		i2c_same_csr_outstanding	2.150s	88.890us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.430s	68.380us	1	1	100.00
		i2c_sec_cm	2.170s	73.400us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.430s	68.380us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.860s	842.895us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.130s	971.903us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.140s	769.884us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.16173351410054561489666080694100863063089225486796684206809224161779997910320
Line 228, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9010130361 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1626908

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.100041679806962360475634481033591581343177286702116242653785905434610589988782
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 971903352 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 971903352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.64149000516354332255188522882770118160516931567703940279796584319897655320417
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10017927542 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10017927542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.1567639735024565563672156503370587413222786495733127621197533204723556246176
    Line 98, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 842895141 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 842895141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.113980655406648518317661033926218622507294823318062707268475898728935317058084
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 769884150 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 769884150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.103433675442271532776998737533086234073432228585827423902211352360327090277895
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 187024686 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```