KEYMGR Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.710s	32.956us	1	1	100.00
V1	random	keymgr_random	4.220s	225.911us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.630s	19.674us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.730s	25.030us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.660s	1.851ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	4.360s	1.653ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.780s	47.668us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.730s	25.030us	1	1	100.00
		keymgr_csr_aliasing	4.360s	1.653ms	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	19.250s	2.377ms	1	1	100.00
V2	sideload	keymgr_sideload	6.130s	311.509us	1	1	100.00
		keymgr_sideload_kmac	2.540s	32.383us	1	1	100.00
		keymgr_sideload_aes	3.180s	37.560us	1	1	100.00
		keymgr_sideload_otbn	2.810s	170.181us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.310s	120.437us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.710s	360.522us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.930s	167.198us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.950s	78.212us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.920s	770.627us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.860s	427.750us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.810s	1.635ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.530s	33.084us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.590s	34.516us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.720s	124.618us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.720s	124.618us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.630s	19.674us	1	1	100.00
		keymgr_csr_rw	1.730s	25.030us	1	1	100.00
		keymgr_csr_aliasing	4.360s	1.653ms	1	1	100.00
		keymgr_same_csr_outstanding	2.510s	92.437us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.630s	19.674us	1	1	100.00
		keymgr_csr_rw	1.730s	25.030us	1	1	100.00
		keymgr_csr_aliasing	4.360s	1.653ms	1	1	100.00
		keymgr_same_csr_outstanding	2.510s	92.437us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
		keymgr_tl_intg_err	3.130s	57.956us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.550s	397.754us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.550s	397.754us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.550s	397.754us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.550s	397.754us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.120s	1.740ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.130s	57.956us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.550s	397.754us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	19.250s	2.377ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.220s	225.911us	1	1	100.00
		keymgr_csr_rw	1.730s	25.030us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.220s	225.911us	1	1	100.00
		keymgr_csr_rw	1.730s	25.030us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.220s	225.911us	1	1	100.00
		keymgr_csr_rw	1.730s	25.030us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.710s	360.522us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.920s	770.627us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.920s	770.627us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.220s	225.911us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.470s	164.632us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.150s	351.906us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.710s	360.522us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.150s	351.906us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.150s	351.906us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.150s	351.906us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.810s	2.648ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.150s	351.906us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.570s	1.316ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.62809545285607164182463043951867951146140778081282451205348772725947770016420
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 1850635979 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 1850635979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.20244645632765205677690664153549445098580634022343748502073071418979824458255
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @  92436824 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @  92436824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.85280732872484818004471989430255684432373755732747447744709091365840004406130
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
        UVM_ERROR @  47667550 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
        UVM_INFO @  47667550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---