KMAC/MASKED Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.360s	12.839ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.960s	21.961us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	27.211us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.430s	1.262ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.200s	199.613us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.780s	1.034ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	27.211us	1	1	100.00
		kmac_csr_aliasing	4.200s	199.613us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.590s	13.149us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.220s	130.782us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	7.319m	62.825ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.413m	12.992ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.080s	1.194ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.970s	4.485ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.985m	46.065ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.110s	969.428us	1	1	100.00
		kmac_test_vectors_shake_128	2.613m	11.533ms	1	1	100.00
		kmac_test_vectors_shake_256	4.824m	23.717ms	1	1	100.00
		kmac_test_vectors_kmac	2.950s	114.077us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.580s	88.615us	1	1	100.00
V2	sideload	kmac_sideload	5.692m	38.099ms	1	1	100.00
V2	app	kmac_app	3.618m	7.345ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.578m	9.416ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.148m	3.415ms	1	1	100.00
V2	error	kmac_error	1.161m	1.654ms	1	1	100.00
V2	key_error	kmac_key_error	7.120s	4.353ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.570s	232.284us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.200s	344.102us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.010s	96.939us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	46.280s	2.455ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.970s	43.163us	1	1	100.00
V2	stress_all	kmac_stress_all	2.706m	15.738ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	23.152us	1	1	100.00
V2	alert_test	kmac_alert_test	1.810s	68.260us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.380s	226.409us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.380s	226.409us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.960s	21.961us	1	1	100.00
		kmac_csr_rw	1.800s	27.211us	1	1	100.00
		kmac_csr_aliasing	4.200s	199.613us	1	1	100.00
		kmac_same_csr_outstanding	2.620s	96.276us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.960s	21.961us	1	1	100.00
		kmac_csr_rw	1.800s	27.211us	1	1	100.00
		kmac_csr_aliasing	4.200s	199.613us	1	1	100.00
		kmac_same_csr_outstanding	2.620s	96.276us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	212.791us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	212.791us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	212.791us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	212.791us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.030s	23.269us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	41.630s	8.823ms	1	1	100.00
		kmac_tl_intg_err	1.720s	8.943us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.720s	8.943us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.970s	43.163us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.360s	12.839ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.692m	38.099ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	212.791us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	41.630s	8.823ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	41.630s	8.823ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	41.630s	8.823ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.360s	12.839ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.970s	43.163us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	41.630s	8.823ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.042m	11.174ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.360s	12.839ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.910s	3.777ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.17738440892934546414512375866038559731985795937433297418945120526666276374001
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  23269412 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  23269412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.5242742703071662599393223331646012072798373210614670207717207283295441083050
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @   8942868 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @   8942868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.97876845180883123245822147687553000286409943108542568099500108046009397455811
      Line 92, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3776510622 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3776510622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---