KMAC/UNMASKED Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.840s	924.261us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	26.595us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.720s	26.183us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.130s	602.818us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.270s	1.510ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.560s	127.017us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	26.183us	1	1	100.00
		kmac_csr_aliasing	7.270s	1.510ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.670s	30.458us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	52.668us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.122m	11.962ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.411m	40.954ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.540s	1.825ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.600s	607.002us	1	1	100.00
		kmac_test_vectors_sha3_384	14.144m	71.973ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.230s	542.452us	1	1	100.00
		kmac_test_vectors_shake_128	1.537m	4.488ms	1	1	100.00
		kmac_test_vectors_shake_256	24.245m	267.455ms	1	1	100.00
		kmac_test_vectors_kmac	2.710s	124.637us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.820s	55.338us	1	1	100.00
V2	sideload	kmac_sideload	1.718m	2.030ms	1	1	100.00
V2	app	kmac_app	2.796m	39.996ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.147m	14.114ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.047m	2.903ms	1	1	100.00
V2	error	kmac_error	28.280s	5.918ms	1	1	100.00
V2	key_error	kmac_key_error	4.650s	5.509ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.020s	93.525us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	26.460s	1.555ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	13.430s	1.549ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	20.500s	7.626ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	4.410s	323.501us	1	1	100.00
V2	stress_all	kmac_stress_all	32.200s	1.690ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.680s	17.740us	1	1	100.00
V2	alert_test	kmac_alert_test	1.570s	94.828us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.290s	72.021us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.290s	72.021us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	26.595us	1	1	100.00
		kmac_csr_rw	1.720s	26.183us	1	1	100.00
		kmac_csr_aliasing	7.270s	1.510ms	1	1	100.00
		kmac_same_csr_outstanding	2.590s	72.409us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	26.595us	1	1	100.00
		kmac_csr_rw	1.720s	26.183us	1	1	100.00
		kmac_csr_aliasing	7.270s	1.510ms	1	1	100.00
		kmac_same_csr_outstanding	2.590s	72.409us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.150s	89.599us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.150s	89.599us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.150s	89.599us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.150s	89.599us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.930s	64.177us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	35.370s	6.286ms	1	1	100.00
		kmac_tl_intg_err	4.910s	775.140us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.910s	775.140us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	4.410s	323.501us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.840s	924.261us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.718m	2.030ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.150s	89.599us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.370s	6.286ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.370s	6.286ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.370s	6.286ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.840s	924.261us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	4.410s	323.501us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.370s	6.286ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.265m	43.285ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.840s	924.261us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	28.490s	1.904ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.95895038898516250228838652116118816074529629137775438693626481323210123577447
      Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1904465673 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1904465673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.98611810487804848330759345464156470963893371628315075706177494449778343054353
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  64177434 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  64177434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---