OTBN Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	40.605us	1	1	100.00
V1	single_binary	otbn_single	9.000s	42.946us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	45.569us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	37.486us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	101.358us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	58.127us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	71.734us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	37.486us	1	1	100.00
		otbn_csr_aliasing	6.000s	58.127us	1	1	100.00
V1	mem_walk	otbn_mem_walk	19.000s	367.881us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	1.252ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	24.000s	141.046us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	328.164us	1	1	100.00
V2	back_to_back	otbn_multi	40.000s	370.110us	1	1	100.00
V2	stress_all	otbn_stress_all	1.050m	268.962us	1	1	100.00
V2	lc_escalation	otbn_escalate	16.000s	51.204us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	14.553us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	92.616us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	55.048us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	21.702us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	445.799us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	445.799us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	45.569us	1	1	100.00
		otbn_csr_rw	6.000s	37.486us	1	1	100.00
		otbn_csr_aliasing	6.000s	58.127us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	124.578us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	45.569us	1	1	100.00
		otbn_csr_rw	6.000s	37.486us	1	1	100.00
		otbn_csr_aliasing	6.000s	58.127us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	124.578us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	11.000s	27.646us	1	1	100.00
		otbn_dmem_err	9.000s	46.751us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	32.367us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	20.827us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	25.944us	1	1	100.00
		otbn_urnd_err	9.000s	14.703us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	32.456us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.596us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	71.280us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
		otbn_tl_intg_err	20.000s	122.973us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	351.089us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	40.605us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	46.751us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	27.646us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	122.973us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	16.000s	51.204us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	27.646us	1	1	100.00
		otbn_dmem_err	9.000s	46.751us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	14.553us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	32.456us	1	1	100.00
		otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	27.646us	1	1	100.00
		otbn_dmem_err	9.000s	46.751us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	14.553us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	32.456us	1	1	100.00
		otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	16.000s	51.204us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	27.646us	1	1	100.00
		otbn_dmem_err	9.000s	46.751us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	14.553us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	32.456us	1	1	100.00
		otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	31.797us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	16.002us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	34.000s	630.615us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	34.000s	630.615us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	22.229us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	72.402us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	58.000s	303.199us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	58.000s	303.199us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	23.815us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	40.000s	370.110us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	62.175us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	42.946us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.583m	18.187ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.167m	869.877us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.28124875788635969144200371615032490295652824913822528752021418134823139729671
      Line 161, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 869877282 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 869877282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.65728283769863311733319197126042819376227542715536847030197651413340009336379
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23815489 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  23815489 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  23815489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---