ROM_CTRL/32KB Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.010s	304.783us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.250s	471.878us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.410s	291.724us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.420s	1.071ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.460s	130.464us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.190s	534.254us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.410s	291.724us	1	1	100.00
		rom_ctrl_csr_aliasing	4.460s	130.464us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.000s	678.638us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.330s	599.843us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.730s	311.495us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	13.200s	458.651us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.920s	7.083ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.290s	203.409us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.520s	470.587us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.520s	470.587us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.250s	471.878us	1	1	100.00
		rom_ctrl_csr_rw	4.410s	291.724us	1	1	100.00
		rom_ctrl_csr_aliasing	4.460s	130.464us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.180s	178.234us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.250s	471.878us	1	1	100.00
		rom_ctrl_csr_rw	4.410s	291.724us	1	1	100.00
		rom_ctrl_csr_aliasing	4.460s	130.464us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.180s	178.234us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	12.680s	425.607us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
		rom_ctrl_tl_intg_err	21.400s	2.243ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.010s	304.783us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.010s	304.783us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.010s	304.783us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	21.400s	2.243ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
		rom_ctrl_kmac_err_chk	9.920s	7.083ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	58.010s	6.283ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	12.680s	425.607us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.517m	1.268ms	1	1	100.00
V2S		TOTAL			4	4	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.700s	493.728us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:691) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.43089217779739969384562335914176821235721568947690003368513494937290410615255
      Line 82, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 493727732 ps: (cip_base_vseq.sv:691) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 493727732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---