ROM_CTRL/64KB Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.510s 1.060ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.410s 212.545us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.660s 1.023ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.850s 490.633us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.670s 289.719us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.660s 574.508us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.660s 1.023ms 1 1 100.00
rom_ctrl_csr_aliasing 7.670s 289.719us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.730s 1.273ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.670s 727.475us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.410s 535.032us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 29.220s 1.098ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.440s 1.194ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.500s 725.777us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.020s 219.278us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.020s 219.278us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.410s 212.545us 1 1 100.00
rom_ctrl_csr_rw 8.660s 1.023ms 1 1 100.00
rom_ctrl_csr_aliasing 7.670s 289.719us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.340s 463.263us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.410s 212.545us 1 1 100.00
rom_ctrl_csr_rw 8.660s 1.023ms 1 1 100.00
rom_ctrl_csr_aliasing 7.670s 289.719us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.340s 463.263us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.670s 3.777ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
rom_ctrl_tl_intg_err 39.520s 475.943us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.510s 1.060ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.510s 1.060ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.510s 1.060ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 39.520s 475.943us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.440s 1.194ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 53.100s 15.457ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.670s 3.777ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.562m 5.996ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.533m 6.190ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00