RV_TIMER Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.746m	291.534ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.570s	17.088us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.500s	62.518us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.890s	1.096ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.580s	103.903us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.620s	53.306us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.500s	62.518us	1	1	100.00
		rv_timer_csr_aliasing	1.580s	103.903us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	19.075m	122.281ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.166m	251.101ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.138m	2.326s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.138m	2.326s	1	1	100.00
V2	stress	rv_timer_stress_all	16.898m	2.149s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.530s	39.713us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.060s	282.290us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.060s	282.290us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.570s	17.088us	1	1	100.00
		rv_timer_csr_rw	1.500s	62.518us	1	1	100.00
		rv_timer_csr_aliasing	1.580s	103.903us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	115.772us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.570s	17.088us	1	1	100.00
		rv_timer_csr_rw	1.500s	62.518us	1	1	100.00
		rv_timer_csr_aliasing	1.580s	103.903us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	115.772us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.710s	130.181us	1	1	100.00
		rv_timer_tl_intg_err	1.980s	84.325us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.980s	84.325us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	11.000s	2.322ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00