SPI_DEVICE/1R1W Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.440m	15.791ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.050s	23.070us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	138.703us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.650s	1.238ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.510s	2.175ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.010s	462.938us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	138.703us	1	1	100.00
		spi_device_csr_aliasing	12.510s	2.175ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	32.739us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.030s	33.125us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	19.309us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.630s	3.082us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	2.050s	12.514us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.520s	44.415us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.520s	44.415us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.090s	1.325ms	1	1	100.00
		spi_device_tpm_sts_read	1.710s	63.457us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.310s	1.991ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.640s	1.718ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.810s	4.271ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.810s	4.271ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.470s	1.503ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.470s	1.503ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.470s	1.503ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.470s	1.503ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.470s	1.503ms	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.090s	565.655us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.460s	429.432us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.460s	429.432us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.460s	429.432us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.560s	805.762us	1	1	100.00
		spi_device_read_buffer_direct	19.310s	11.445ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.460s	429.432us	1	1	100.00
		spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	quad_spi	spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	dual_spi	spi_device_flash_all	11.650s	891.627us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.020s	147.004us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.020s	147.004us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.440m	15.791ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.999m	40.170ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.140s	65.026us	1	1	100.00
V2	alert_test	spi_device_alert_test	2.040s	106.471us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.520s	14.184us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.580s	123.405us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.580s	123.405us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.050s	23.070us	1	1	100.00
		spi_device_csr_rw	2.690s	138.703us	1	1	100.00
		spi_device_csr_aliasing	12.510s	2.175ms	1	1	100.00
		spi_device_same_csr_outstanding	3.340s	239.418us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.050s	23.070us	1	1	100.00
		spi_device_csr_rw	2.690s	138.703us	1	1	100.00
		spi_device_csr_aliasing	12.510s	2.175ms	1	1	100.00
		spi_device_same_csr_outstanding	3.340s	239.418us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.230s	337.313us	1	1	100.00
		spi_device_tl_intg_err	5.560s	134.413us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.560s	134.413us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.650s	22.820us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.75653233185587401814994889885591180827581466637104636008933139609702827478342
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2642822 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[45])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2642822 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2642822 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[941])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.57661080878262295722975190215569600832610013578374017044382303640165815515410
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  12035356 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  12035356 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @  12125356 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7fdadb [11111111101101011011011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @  12125356 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x7fdadb [11111111101101011011011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])