SPI_HOST Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.067m	6.022ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	20.564us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	19.053us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	1.663ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	28.098us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	83.647us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	19.053us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.098us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	25.707us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	23.579us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	32.194us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	588.158us	1	1	100.00
		spi_host_error_cmd	4.000s	35.708us	1	1	100.00
		spi_host_event	23.000s	2.709ms	1	1	100.00
V2	clock_rate	spi_host_speed	8.000s	1.164ms	1	1	100.00
V2	speed	spi_host_speed	8.000s	1.164ms	1	1	100.00
V2	chip_select_timing	spi_host_speed	8.000s	1.164ms	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	25.622us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	629.598us	1	1	100.00
V2	cpol_cpha	spi_host_speed	8.000s	1.164ms	1	1	100.00
V2	full_cycle	spi_host_speed	8.000s	1.164ms	1	1	100.00
V2	duplex	spi_host_smoke	1.067m	6.022ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.067m	6.022ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.067m	3.460ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.483ms	1	1	100.00
V2	stall	spi_host_status_stall	22.000s	3.686ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	8.000s	1.089ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	588.158us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	38.977us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	19.560us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	151.181us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	151.181us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	20.564us	1	1	100.00
		spi_host_csr_rw	4.000s	19.053us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.098us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	29.007us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	20.564us	1	1	100.00
		spi_host_csr_rw	4.000s	19.053us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.098us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	29.007us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	170.524us	1	1	100.00
		spi_host_sec_cm	4.000s	58.834us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	170.524us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	47.883m	149.488ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.104047378144880269020030101808918280532334025742457163567020162821089532984466
      Line 186, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 149488427058 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x12e47dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
        UVM_INFO @ 149488427058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---