SRAM_CTRL/MAIN Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	35.180s	4.643ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	42.030us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.600s	17.324us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.160s	44.189us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.740s	50.528us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.790s	356.517us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.600s	17.324us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	50.528us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.217m	35.895ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.992m	34.031ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.038m	4.000ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.047m	3.049ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.234m	404.675ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	15.875m	82.153ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	39.850s	9.848ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.004m	24.128ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.990s	2.126ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.296m	21.676ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.430s	695.188us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.750s	713.374us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.770s	738.975us	1	1	100.00
V2	regwen	sram_ctrl_regwen	15.237m	21.214ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.150s	918.914us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.069m	211.223ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.470s	59.294us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.250s	278.377us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.250s	278.377us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	42.030us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	17.324us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	50.528us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.600s	22.030us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	42.030us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	17.324us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	50.528us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.600s	22.030us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.590s	7.367ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
		sram_ctrl_tl_intg_err	2.950s	1.471ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.950s	1.471ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.237m	21.214ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.237m	21.214ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.600s	17.324us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.004m	24.128ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.004m	24.128ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.004m	24.128ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	39.850s	9.848ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.110s	704.400us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.590s	7.367ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.490s	1.337ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	35.180s	4.643ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	35.180s	4.643ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.004m	24.128ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	39.850s	9.848ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	35.180s	4.643ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.640s	7.049us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	47.960s	5.904ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.78468611033003602431443076545043786857971055948656946269556033349533635441473
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7049405 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7049405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---