SRAM_CTRL/RET Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.680s	159.723us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.810s	46.108us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.680s	37.005us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.040s	93.797us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.750s	27.012us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.030s	148.974us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.680s	37.005us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	27.012us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.580s	1.074ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.730s	91.342us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.941m	58.914ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.707m	9.185ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	46.530s	15.611ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.414m	3.239ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.160s	1.720ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.451m	5.118ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.280s	488.030us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.800m	3.051ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	54.120s	536.821us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.004m	2.421ms	1	1	100.00
		sram_ctrl_throughput_w_readback	9.210s	90.842us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.090m	3.960ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.820s	67.719us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.486m	29.828ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.690s	31.924us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.710s	30.347us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.710s	30.347us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.810s	46.108us	1	1	100.00
		sram_ctrl_csr_rw	1.680s	37.005us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	27.012us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	38.313us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.810s	46.108us	1	1	100.00
		sram_ctrl_csr_rw	1.680s	37.005us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	27.012us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	38.313us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.050s	3.342ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
		sram_ctrl_tl_intg_err	2.230s	189.371us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.230s	189.371us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.090m	3.960ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.090m	3.960ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.680s	37.005us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.451m	5.118ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.451m	5.118ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.451m	5.118ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.160s	1.720ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.730s	73.047us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.050s	3.342ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.930s	205.396us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.680s	159.723us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.680s	159.723us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.451m	5.118ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.160s	1.720ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.680s	159.723us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	3.803us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.401m	1.709ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.35208240619164329767382162026263081661754548240989525464066830239555483214029
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3802829 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3802829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---