UART Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.330s	674.016us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.560s	15.699us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.460s	14.324us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.250s	114.448us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.600s	25.839us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.660s	30.316us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.460s	14.324us	1	1	100.00
		uart_csr_aliasing	1.600s	25.839us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	21.930s	101.906ms	1	1	100.00
V2	parity	uart_smoke	2.330s	674.016us	1	1	100.00
		uart_tx_rx	21.930s	101.906ms	1	1	100.00
V2	parity_error	uart_intr	15.600s	13.685ms	1	1	100.00
		uart_rx_parity_err	32.600s	92.941ms	1	1	100.00
V2	watermark	uart_tx_rx	21.930s	101.906ms	1	1	100.00
		uart_intr	15.600s	13.685ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.730s	14.342ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	6.452m	166.440ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	11.320s	8.335ms	1	1	100.00
V2	rx_frame_err	uart_intr	15.600s	13.685ms	1	1	100.00
V2	rx_break_err	uart_intr	15.600s	13.685ms	1	1	100.00
V2	rx_timeout	uart_intr	15.600s	13.685ms	1	1	100.00
V2	perf	uart_perf	1.711m	12.274ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.670s	1.743ms	1	1	100.00
V2	line_loopback	uart_loopback	3.670s	1.743ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	20.380s	17.475ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.670s	44.989ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	15.320s	6.303ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	39.720s	6.399ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.679m	37.470ms	1	1	100.00
V2	stress_all	uart_stress_all	2.862m	278.658ms	1	1	100.00
V2	alert_test	uart_alert_test	1.500s	40.892us	1	1	100.00
V2	intr_test	uart_intr_test	1.570s	37.025us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.110s	679.641us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.110s	679.641us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.560s	15.699us	1	1	100.00
		uart_csr_rw	1.460s	14.324us	1	1	100.00
		uart_csr_aliasing	1.600s	25.839us	1	1	100.00
		uart_same_csr_outstanding	1.560s	72.138us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.560s	15.699us	1	1	100.00
		uart_csr_rw	1.460s	14.324us	1	1	100.00
		uart_csr_aliasing	1.600s	25.839us	1	1	100.00
		uart_same_csr_outstanding	1.560s	72.138us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.780s	68.669us	1	1	100.00
		uart_tl_intg_err	1.960s	169.234us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.960s	169.234us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.800s	43.516ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00