CHIP Simulation Results

Monday April 21 2025 17:00:25 UTC

GitHub Revision: `47374bd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.268m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.268m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	22.823s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	20.375s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	15.133s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.220m	5.931ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.220m	5.931ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.220m	5.931ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	2.792m		0	1	0.00
		chip_sw_example_manufacturer	29.256s		0	1	0.00
		chip_sw_example_concurrency	5.023m	4.775ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.124s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.760s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.750s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.750s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.850s	58.961us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.089m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.952m	9.741ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.356m	5.532ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	17.405s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.215s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.127s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.601s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.540s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.540s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.611m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.491m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.909m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.909m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.018m	3.109ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.090m	3.339ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.194m	15.238ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.030s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.978s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	20.515m	31.307ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.179m	6.760ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.680m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.680m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.258s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.557s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.557s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	17.656s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.508m	3.576ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.147m	5.034ms	1	1	100.00
		chip_sw_aes_idle	4.561m	4.099ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.192m	4.699ms	1	1	100.00
		chip_sw_kmac_idle	3.725m	4.036ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.323s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.346s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.641s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.536s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.050s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.342s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.313s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.540s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.050s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.342s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.313s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.442s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.456m	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.600s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.960s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	51.460s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.089s		0	1	0.00
		chip_sw_clkmgr_jitter	3.986m	4.576ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.216m	5.577ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.531s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.460s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	54.060s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	55.610s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	46.380s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	48.060s	10.120us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.183s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.368s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.822s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.370s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.200m	16.108ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	16.557s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.014s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.200m	16.108ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	17.866s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	22.605s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.695s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	27.266s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.064s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.194m	15.238ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.287m	20.020ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.110m	8.830ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.506m	30.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.837m	4.157ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.351s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.245s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.139s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.506m	30.016ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.698s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	15.940s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.380s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.246s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.492s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.880s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.245s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.124s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.652m	10.730ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.211s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.462s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.308s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	17.943s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.650m	8.598ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.155m	13.262ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.894s		0	1	0.00
		chip_prim_tl_access	4.848m	5.617ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.050s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.342s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.313s		0	1	0.00
		chip_rv_dm_lc_disabled	20.515m	31.307ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.296m	3.909ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.456m	10.300us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.545m	4.414ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.561m	4.099ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.982m	4.791ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.600s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.192m	4.699ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.760m	4.428ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.634m	5.076ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	51.460s	10.340us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.650m	8.598ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.370s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.657m	5.297ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.725m	4.036ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.565s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.565s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.276s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.497m	5.291ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.832s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.650m	8.598ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.960s	10.120us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.852s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.442s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.147m	5.034ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.147m	5.034ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.147m	5.034ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.467m	6.298ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.155m	13.262ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.155m	13.262ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.985m	6.499ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.089s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.894s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.909m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.467m	6.298ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.650m	8.598ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.985m	6.499ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.657m	3.555ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.467m	6.298ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.650m	8.598ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.985m	6.499ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.657m	3.555ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.137s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.124s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.211s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.462s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.308s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	17.943s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.821s		0	1	0.00
		chip_prim_tl_access	4.848m	5.617ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.848m	5.617ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	32.726s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	17.809s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.368s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.442s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.456m	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.600s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.960s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	51.460s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.089s		0	1	0.00
		chip_sw_clkmgr_jitter	3.986m	4.576ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.297m	10.344ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.297m	10.344ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.059m	4.632ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.868m	4.405ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.913m	5.501ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.419m	4.732ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.286m	4.094ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.692m	3.850ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.657m	3.555ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.287m	20.020ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.287m	20.020ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.842m	3.824ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.117m	4.932ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.474m	3.866ms	1	1	100.00
		chip_sw_csrng_smoketest	3.510m	5.703ms	1	1	100.00
		chip_sw_gpio_smoketest	3.583m	3.706ms	1	1	100.00
		chip_sw_hmac_smoketest	3.520m	3.435ms	1	1	100.00
		chip_sw_kmac_smoketest	3.952m	4.451ms	1	1	100.00
		chip_sw_otbn_smoketest	4.462m	5.650ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.448m	3.718ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.244m	4.529ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.561m	6.290ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.944m	3.611ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.096m	4.536ms	1	1	100.00
		chip_sw_uart_smoketest	3.368m	4.343ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	16.586s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.124s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.089m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.973s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.298m	4.637ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.005m	5.746ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.647m	4.144ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.704m	3.682ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.528s		0	1	0.00
		chip_rv_dm_lc_disabled	20.515m	31.307ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.102s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.594s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.819s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.711s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.528s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.655s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	14.473s		0	1	0.00
		rom_volatile_raw_unlock	10.457s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	22.688s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.002m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.192m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.341m	4.270ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.341m	4.270ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.750s		0	1	0.00
		chip_same_csr_outstanding	10.370s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.750s		0	1	0.00
		chip_same_csr_outstanding	10.370s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.557m	399.171us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.980s	11.985us	1	1	100.00
		xbar_smoke_large_delays	4.388m	2.247ms	1	1	100.00
		xbar_smoke_slow_rsp	5.364m	1.996ms	1	1	100.00
		xbar_random_zero_delays	12.250s	14.451us	1	1	100.00
		xbar_random_large_delays	23.726m	12.464ms	1	1	100.00
		xbar_random_slow_rsp	4.112m	1.524ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	56.510s	86.813us	1	1	100.00
		xbar_error_and_unmapped_addr	1.173m	171.987us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	49.590s	48.039us	1	1	100.00
		xbar_error_and_unmapped_addr	1.173m	171.987us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.802m	654.242us	1	1	100.00
		xbar_access_same_device_slow_rsp	18.898m	6.835ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	53.180s	134.970us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.729m	1.556ms	1	1	100.00
		xbar_stress_all_with_error	21.356m	3.603ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.183m	499.824us	1	1	100.00
		xbar_stress_all_with_reset_error	28.888m	4.567ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.826s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.393s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.782s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.278s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.721s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.523s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.503s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.168s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.583s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.889s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.321s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.622s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.720s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.369s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.908s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	14.674s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.062s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.598s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.682s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.083s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.430s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.943s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.875s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.685s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.030s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.005s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.584s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.705s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.085s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.363s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.214s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	10.873s		0	1	0.00
		rom_e2e_asm_init_dev	12.809s		0	1	0.00
		rom_e2e_asm_init_prod	12.325s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.591s		0	1	0.00
		rom_e2e_asm_init_rma	11.003s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.638s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.436s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.537s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.017s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.861m	3.434ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.480m	3.653ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.126s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.901s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.548s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.281s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.711m	14.722ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.212s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.498m	12.441ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.149s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.633s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.126s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.901s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.548s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.616s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.675s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.758s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.212m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.584m	13.776ms	1	1	100.00
		chip_plic_all_irqs_0	8.787m	7.061ms	1	1	100.00
		chip_plic_all_irqs_10	9.788m	6.243ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.327m	6.034ms	1	1	100.00
		chip_sw_dma_abort	4.397m	3.923ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.740s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.510s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.876s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.137s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.448s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.961s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.680s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.357s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.388s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.855s		0	1	0.00
		chip_sw_mbx_smoketest	4.824m	6.001ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.20959132160547683176848520065895825793873569195349514482278105540521483188420
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (0a2ce4)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (0e3120)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 151.657s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.84388756354947788367102361257704196589986421813679410539219116578399083630673
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (70b6d2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.883s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.113291729928903762816192407973114281055562342605883739573027708170732256013750
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (6cada1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.333s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.88273968037347910681973428246456188798809808232179649350947041608407562966145
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (8d3140)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 86.197s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.4654041910716179499946350191022227772078265976792950361390604450940915100936
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f3488a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.188s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.104616405492128329263417820896228827576045129672175059846849828817542531739206
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.50450007137185897038564662324831256205938007388446072112519519595339938148043
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.34864408106009858103273097014999809283297601752567485483254364169588143283741
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.11550364070750254860317264547822339648202922002872283380440388760153551195476
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.81691078031482768799375095194190837262276147493007153368391235071557287629099
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.94113973274815743667057448757570075785740345725278841875032721987223715606544
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.62893298978040263881554286387507656025043959100078256054214113228782954953601
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.92612096299606136838301903043055837548374571803302684433633743767381876306170
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.67881895325585116410203225320345461267306302497605914185220549533339665873330
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.913475 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.913475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.103448753230000227001403206010878562656633996846864470277805791808438169674662
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20020.103568 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20020.103568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.43384263832027378246619705637470582341502949330172359931304523797192113825795
Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.030236 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.030236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.5918641241415415880964809359035292314599984099163938241684235954559932535956
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8597.724350 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (84371990509508487281327579522899301401119944392470288173228602416663576875058 [0xba88dab56fa401016ad3161941588fae468f4f6854a7286ba2f5bf251e769032] vs 36443739566717340927152519509906023842547939972431735197647575021594109880990 [0x50926cf58c9763be5a7fdab03704b2c6cccc409bfc4cb85d0fa8007d14f52a9e])
  UVM_INFO @ 8597.724350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.24622241215885010572273937458643327118662156787533024848740667378475467092955
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10729.703622 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (26494009954200770582760202143806248967730070807339138189095388128301546246903 [0x3a931406c8f2a843246593b31c0aa77577a422a3630449066f9e1c6e812c92f7] vs 43387554072878374963206018073425103537318795670811438746892644604805059167747 [0x5fec7c404dd5451d3ccbc7fe412d6166da8d6753642a0f3c2379bc4396bfc603])
  UVM_INFO @ 10729.703622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.30431720695610865314841322476969695264345870380647494945167680595850460538346
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3108.805209 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hdf6cd7e6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h0  a_user: 'h2696b  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3108.805209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.99677389301854363148875489919066797022276777159239576580247949861376807946651
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3338.639397 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hdc359063  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h1  a_user: 'h248b0  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3338.639397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.65443920526001061961354687107678564370673056120270297135135576577878108039086
    Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5532.481600 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5532.481600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.7438347348904702028557909807963671712498685295112210623886304047187936327184
    Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4632.225458 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4632.225458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.77116035786024675906598136600129972893057126245890073851396568048850237708525
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4731.758096 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4731.758096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.62720689032231407283960787310427203722927368970335905287974465600324608232006
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.7400328695674179752573769872425429450328484301176803802353688992305561671901
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4269.904316 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4269.904316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.47745480983058633880106114792895496442097393597413407378873231908257266326113
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15238.280812 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15238.280812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.689396164683262411416565384094777929678466445049559760624805736897046670552
    Line 310, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.74480290653121438489813858653274797743005062738712071393917772472473272469453
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3923.041808 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3923.041808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```