DMA Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	296.933us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.104ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	2.554ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	70.432us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	52.781us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	5.698ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	521.204us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	196.767us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	52.781us	1	1	100.00
		dma_csr_aliasing	10.000s	521.204us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.483m	20.735ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.417m	60.009ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.550m	76.400ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	19.800m	107.313ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.417m	60.009ms	1	1	100.00
V2	dma_abort	dma_abort	17.000s	2.032ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.117m	17.156ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	22.107us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	92.660us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	92.660us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	70.432us	1	1	100.00
		dma_csr_rw	4.000s	52.781us	1	1	100.00
		dma_csr_aliasing	10.000s	521.204us	1	1	100.00
		dma_same_csr_outstanding	5.000s	230.079us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	70.432us	1	1	100.00
		dma_csr_rw	4.000s	52.781us	1	1	100.00
		dma_csr_aliasing	10.000s	521.204us	1	1	100.00
		dma_same_csr_outstanding	5.000s	230.079us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	28.000s	391.858us	1	1	100.00
		dma_generic_stress	19.800m	107.313ms	1	1	100.00
		dma_handshake_stress	2.417m	60.009ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	523.084us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.650m	67.038ms	1	1	100.00
		dma_longer_transfer	29.000s	8.403ms	1	1	100.00
		TOTAL			21	21	100.00