EDN Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.710s	15.415us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.550s	39.296us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.570s	41.890us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.140s	112.471us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.830s	262.228us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.520s	80.297us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.570s	41.890us	1	1	100.00
		edn_csr_aliasing	1.830s	262.228us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.490s	163.120us	1	1	100.00
V2	csrng_commands	edn_genbits	2.490s	163.120us	1	1	100.00
V2	genbits	edn_genbits	2.490s	163.120us	1	1	100.00
V2	interrupts	edn_intr	1.540s	23.627us	1	1	100.00
V2	alerts	edn_alert	1.800s	54.890us	1	1	100.00
V2	errs	edn_err	1.800s	25.177us	1	1	100.00
V2	disable	edn_disable	1.730s	31.115us	1	1	100.00
		edn_disable_auto_req_mode	1.890s	36.325us	1	1	100.00
V2	stress_all	edn_stress_all	3.640s	211.121us	1	1	100.00
V2	intr_test	edn_intr_test	1.690s	12.180us	1	1	100.00
V2	alert_test	edn_alert_test	1.760s	155.703us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.110s	447.846us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.110s	447.846us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.550s	39.296us	1	1	100.00
		edn_csr_rw	1.570s	41.890us	1	1	100.00
		edn_csr_aliasing	1.830s	262.228us	1	1	100.00
		edn_same_csr_outstanding	1.690s	19.004us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.550s	39.296us	1	1	100.00
		edn_csr_rw	1.570s	41.890us	1	1	100.00
		edn_csr_aliasing	1.830s	262.228us	1	1	100.00
		edn_same_csr_outstanding	1.690s	19.004us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.980s	417.449us	1	1	100.00
		edn_tl_intg_err	2.190s	87.966us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.650s	19.887us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.800s	54.890us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.980s	417.449us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.980s	417.449us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.980s	417.449us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.980s	417.449us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.800s	54.890us	1	1	100.00
		edn_sec_cm	3.980s	417.449us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.800s	54.890us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.190s	87.966us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	32.730s	18.141ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00