HMAC Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.160s 5.185ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.700s 34.855us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.710s 25.559us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.310s 3.088ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.660s 1.860ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.970s 18.242us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.710s 25.559us 1 1 100.00
hmac_csr_aliasing 6.660s 1.860ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 43.050s 3.686ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.208m 3.706ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.909m 5.461ms 1 1 100.00
hmac_test_sha384_vectors 20.120s 924.750us 1 1 100.00
hmac_test_sha512_vectors 20.560s 308.373us 1 1 100.00
hmac_test_hmac256_vectors 9.170s 1.196ms 1 1 100.00
hmac_test_hmac384_vectors 8.610s 221.581us 1 1 100.00
hmac_test_hmac512_vectors 9.420s 1.363ms 1 1 100.00
V2 burst_wr hmac_burst_wr 19.560s 6.395ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 48.840s 1.938ms 1 1 100.00
V2 error hmac_error 1.267m 2.067ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 41.320s 18.230ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.160s 5.185ms 1 1 100.00
hmac_long_msg 43.050s 3.686ms 1 1 100.00
hmac_back_pressure 1.208m 3.706ms 1 1 100.00
hmac_datapath_stress 48.840s 1.938ms 1 1 100.00
hmac_burst_wr 19.560s 6.395ms 1 1 100.00
hmac_stress_all 3.440m 22.898ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.160s 5.185ms 1 1 100.00
hmac_long_msg 43.050s 3.686ms 1 1 100.00
hmac_back_pressure 1.208m 3.706ms 1 1 100.00
hmac_datapath_stress 48.840s 1.938ms 1 1 100.00
hmac_wipe_secret 41.320s 18.230ms 1 1 100.00
hmac_test_sha256_vectors 2.909m 5.461ms 1 1 100.00
hmac_test_sha384_vectors 20.120s 924.750us 1 1 100.00
hmac_test_sha512_vectors 20.560s 308.373us 1 1 100.00
hmac_test_hmac256_vectors 9.170s 1.196ms 1 1 100.00
hmac_test_hmac384_vectors 8.610s 221.581us 1 1 100.00
hmac_test_hmac512_vectors 9.420s 1.363ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.160s 5.185ms 1 1 100.00
hmac_long_msg 43.050s 3.686ms 1 1 100.00
hmac_back_pressure 1.208m 3.706ms 1 1 100.00
hmac_datapath_stress 48.840s 1.938ms 1 1 100.00
hmac_burst_wr 19.560s 6.395ms 1 1 100.00
hmac_error 1.267m 2.067ms 1 1 100.00
hmac_wipe_secret 41.320s 18.230ms 1 1 100.00
hmac_test_sha256_vectors 2.909m 5.461ms 1 1 100.00
hmac_test_sha384_vectors 20.120s 924.750us 1 1 100.00
hmac_test_sha512_vectors 20.560s 308.373us 1 1 100.00
hmac_test_hmac256_vectors 9.170s 1.196ms 1 1 100.00
hmac_test_hmac384_vectors 8.610s 221.581us 1 1 100.00
hmac_test_hmac512_vectors 9.420s 1.363ms 1 1 100.00
hmac_stress_all 3.440m 22.898ms 1 1 100.00
V2 stress_all hmac_stress_all 3.440m 22.898ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 42.009us 1 1 100.00
V2 intr_test hmac_intr_test 1.480s 36.622us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.720s 255.072us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.720s 255.072us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.700s 34.855us 1 1 100.00
hmac_csr_rw 1.710s 25.559us 1 1 100.00
hmac_csr_aliasing 6.660s 1.860ms 1 1 100.00
hmac_same_csr_outstanding 1.950s 22.854us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.700s 34.855us 1 1 100.00
hmac_csr_rw 1.710s 25.559us 1 1 100.00
hmac_csr_aliasing 6.660s 1.860ms 1 1 100.00
hmac_same_csr_outstanding 1.950s 22.854us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.840s 427.241us 1 1 100.00
hmac_tl_intg_err 2.430s 249.912us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.430s 249.912us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.160s 5.185ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.340s 286.771us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 30.780s 2.765ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.860s 137.089us 1 1 100.00
TOTAL 28 28 100.00