I2C Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: `ebd55f1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	54.570s	7.319ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.800s	635.274us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	19.659us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.690s	28.656us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.530s	273.518us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.100s	200.503us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.710s	32.961us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.690s	28.656us	1	1	100.00
		i2c_csr_aliasing	2.100s	200.503us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.360s	940.573us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.771m	13.234ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	14.210s	5.246ms	1	1	100.00
V2	host_override	i2c_host_override	1.710s	84.549us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.285m	8.103ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.772m	9.475ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.040s	861.747us	1	1	100.00
		i2c_host_fifo_fmt_empty	10.430s	314.334us	1	1	100.00
		i2c_host_fifo_reset_rx	10.500s	714.168us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.249m	2.173ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	16.460s	568.422us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.630s	332.735us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.240s	8.484ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.332m	21.709ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.700s	742.124us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.750s	1.015ms	1	1	100.00
		i2c_target_intr_smoke	7.180s	1.348ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.560s	165.433us	1	1	100.00
		i2c_target_fifo_reset_tx	2.170s	623.271us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.137m	28.320ms	1	1	100.00
		i2c_target_stress_rd	8.750s	1.015ms	1	1	100.00
		i2c_target_intr_stress_wr	35.770s	15.873ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.670s	3.260ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	14.910s	10.012ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.820s	4.865ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	9.440s	10.056ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.830s	787.511us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.200s	266.145us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	14.210s	5.246ms	1	1	100.00
		i2c_host_perf_precise	4.810s	960.567us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	16.460s	568.422us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.600s	756.355us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.710s	902.801us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.950s	2.812ms	1	1	100.00
		i2c_target_nack_txstretch	2.250s	137.518us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.820s	404.650us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.560s	1.792ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.390s	18.537us	1	1	100.00
V2	intr_test	i2c_intr_test	1.540s	41.927us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.310s	304.844us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.310s	304.844us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	19.659us	1	1	100.00
		i2c_csr_rw	1.690s	28.656us	1	1	100.00
		i2c_csr_aliasing	2.100s	200.503us	1	1	100.00
		i2c_same_csr_outstanding	2.030s	22.783us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	19.659us	1	1	100.00
		i2c_csr_rw	1.690s	28.656us	1	1	100.00
		i2c_csr_aliasing	2.100s	200.503us	1	1	100.00
		i2c_same_csr_outstanding	2.030s	22.783us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.150s	150.324us	1	1	100.00
		i2c_sec_cm	2.000s	283.692us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.150s	150.324us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.590s	303.123us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.060s	546.063us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	35.820s	1.669ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.73657455688426595887540356183894159328096866458202327533416088885720492914213
Line 129, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13233589303 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5991214

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.36890060718571684563757594031143550710689969156342580674161081348306859185575
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 332735264 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @151457

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
- Test i2c_target_stretch has 1 failures.
  - 0.i2c_target_stretch.10293874788508279392383108059329625040137880776989942798138151984477348808303
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011757353 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011757353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.92042053563127080709415738267741945580689079804891969024251082600949939275258
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 546063081 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 4 [0x4])
  UVM_INFO @ 546063081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.15519829499183117054406813063328652479845520629197855813553431284934629440671
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10056092308 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10056092308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.12731681677669781071459913996596488411849215298838037875084447340396284659036
    Line 120, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 303122758 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 303122758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.14877322599931285455157919180403322164503620193165859867028062657583127429496
    Line 111, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1668811169 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1668811169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```