KEYMGR Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.500s	143.043us	1	1	100.00
V1	random	keymgr_random	4.080s	86.273us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	64.153us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.600s	44.678us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.860s	133.100us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	2.330s	367.372us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.810s	120.710us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.600s	44.678us	0	1	0.00
		keymgr_csr_aliasing	2.330s	367.372us	0	1	0.00
V1		TOTAL			4	7	57.14
V2	cfgen_during_op	keymgr_cfg_regwen	4.040s	209.553us	1	1	100.00
V2	sideload	keymgr_sideload	3.360s	214.341us	1	1	100.00
		keymgr_sideload_kmac	3.750s	153.230us	1	1	100.00
		keymgr_sideload_aes	4.030s	150.366us	1	1	100.00
		keymgr_sideload_otbn	2.910s	195.318us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.020s	48.040us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.420s	322.820us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.730s	103.682us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.950s	126.427us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.510s	406.073us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.610s	98.482us	1	1	100.00
V2	stress_all	keymgr_stress_all	2.992m	24.083ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.560s	19.073us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.630s	13.807us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.180s	214.234us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.180s	214.234us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	64.153us	1	1	100.00
		keymgr_csr_rw	1.600s	44.678us	0	1	0.00
		keymgr_csr_aliasing	2.330s	367.372us	0	1	0.00
		keymgr_same_csr_outstanding	1.610s	56.754us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	64.153us	1	1	100.00
		keymgr_csr_rw	1.600s	44.678us	0	1	0.00
		keymgr_csr_aliasing	2.330s	367.372us	0	1	0.00
		keymgr_same_csr_outstanding	1.610s	56.754us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
		keymgr_tl_intg_err	4.320s	191.435us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.470s	102.388us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.470s	102.388us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.470s	102.388us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.470s	102.388us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.710s	22.078us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.320s	191.435us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.470s	102.388us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.040s	209.553us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.080s	86.273us	1	1	100.00
		keymgr_csr_rw	1.600s	44.678us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.080s	86.273us	1	1	100.00
		keymgr_csr_rw	1.600s	44.678us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.080s	86.273us	1	1	100.00
		keymgr_csr_rw	1.600s	44.678us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.420s	322.820us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.510s	406.073us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.510s	406.073us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.080s	86.273us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.200s	107.064us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.940s	102.755us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.420s	322.820us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.940s	102.755us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.940s	102.755us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.940s	102.755us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.980s	474.127us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.940s	102.755us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.930s	431.449us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	30	83.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 5 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.34143234519561569691336883897600551601972505956345533790495045058188493872458
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  22078060 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  22078060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.65991641529170191746635827124754170921975775847392848143760382119480884773748
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
        UVM_ERROR @  44677605 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
        UVM_INFO @  44677605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.114431277362352605171437259175417892275108122613582064931211449870094275822502
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
        UVM_ERROR @ 367372315 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
        UVM_INFO @ 367372315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.83058181190429786845972964685061938570863610032171691741712382796644839335703
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @  56754465 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @  56754465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.42498331478113394948636989828319248834296957924379834879871589344079858440237
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @ 120709547 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @ 120709547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---