KMAC/MASKED Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	57.760s	3.244ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	29.398us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.720s	46.571us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.910s	2.101ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.780s	285.805us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	598.909us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	46.571us	1	1	100.00
		kmac_csr_aliasing	5.780s	285.805us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.690s	19.173us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	17.732us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	31.713m	145.693ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.980s	331.575us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.607m	379.682ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.108m	61.573ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.630m	117.533ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.171m	164.034ms	1	1	100.00
		kmac_test_vectors_shake_128	2.000m	19.373ms	1	1	100.00
		kmac_test_vectors_shake_256	5.141m	388.143ms	1	1	100.00
		kmac_test_vectors_kmac	3.920s	267.294us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.710s	393.344us	1	1	100.00
V2	sideload	kmac_sideload	2.948m	3.717ms	1	1	100.00
V2	app	kmac_app	2.250m	12.695ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.139m	48.724ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	23.510s	11.025ms	1	1	100.00
V2	error	kmac_error	4.806m	4.820ms	1	1	100.00
V2	key_error	kmac_key_error	6.420s	864.052us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.920s	218.148us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.990s	4.190ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.820s	16.042us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	46.700s	23.975ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.910s	64.721us	1	1	100.00
V2	stress_all	kmac_stress_all	17.260s	916.957us	1	1	100.00
V2	intr_test	kmac_intr_test	1.550s	75.145us	1	1	100.00
V2	alert_test	kmac_alert_test	1.830s	12.031us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.910s	88.759us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.910s	88.759us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	29.398us	1	1	100.00
		kmac_csr_rw	1.720s	46.571us	1	1	100.00
		kmac_csr_aliasing	5.780s	285.805us	1	1	100.00
		kmac_same_csr_outstanding	2.530s	1.174ms	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	29.398us	1	1	100.00
		kmac_csr_rw	1.720s	46.571us	1	1	100.00
		kmac_csr_aliasing	5.780s	285.805us	1	1	100.00
		kmac_same_csr_outstanding	2.530s	1.174ms	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.920s	38.716us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.920s	38.716us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.920s	38.716us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.920s	38.716us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.980s	62.590us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	45.740s	4.768ms	1	1	100.00
		kmac_tl_intg_err	1.980s	13.096us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.980s	13.096us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.910s	64.721us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	57.760s	3.244ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.948m	3.717ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.920s	38.716us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	45.740s	4.768ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	45.740s	4.768ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	45.740s	4.768ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	57.760s	3.244ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.910s	64.721us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	45.740s	4.768ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.333m	3.825ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	57.760s	3.244ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.060s	1.339ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.88922860861006203980654262516300040953506436795493717616150457585175125559209
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  62590222 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1342893797 [0x500aeee5] vs 2639060825 [0x9d4cdf59]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
        UVM_INFO @  62590222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.93306994272386773254775148829820664245830354673162317143676515839228971852845
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  13095831 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  13095831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---