KMAC/UNMASKED Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.360s	4.183ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.740s	17.711us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.040s	242.845us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.370s	150.816us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.960s	382.751us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.910s	125.891us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.040s	242.845us	1	1	100.00
		kmac_csr_aliasing	6.960s	382.751us	1	1	100.00
V1	mem_walk	kmac_mem_walk	2.000s	37.122us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.360s	44.566us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.380m	27.348ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.221m	24.962ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.760s	10.281ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.810s	1.741ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.740s	1.213ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.707m	120.234ms	1	1	100.00
		kmac_test_vectors_shake_128	1.680m	7.371ms	1	1	100.00
		kmac_test_vectors_shake_256	18.004m	17.236ms	1	1	100.00
		kmac_test_vectors_kmac	2.930s	1.003ms	1	1	100.00
		kmac_test_vectors_kmac_xof	3.240s	77.484us	1	1	100.00
V2	sideload	kmac_sideload	1.164m	2.559ms	1	1	100.00
V2	app	kmac_app	1.209m	10.172ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.327m	27.320ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	35.740s	7.849ms	1	1	100.00
V2	error	kmac_error	14.840s	4.192ms	1	1	100.00
V2	key_error	kmac_key_error	6.260s	1.424ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.530s	148.640us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.060s	1.526ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.010s	862.828us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	15.620s	4.276ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.250s	33.908us	1	1	100.00
V2	stress_all	kmac_stress_all	3.295m	20.357ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.670s	22.667us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	19.060us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.660s	150.638us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.660s	150.638us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.740s	17.711us	1	1	100.00
		kmac_csr_rw	2.040s	242.845us	1	1	100.00
		kmac_csr_aliasing	6.960s	382.751us	1	1	100.00
		kmac_same_csr_outstanding	2.630s	127.474us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.740s	17.711us	1	1	100.00
		kmac_csr_rw	2.040s	242.845us	1	1	100.00
		kmac_csr_aliasing	6.960s	382.751us	1	1	100.00
		kmac_same_csr_outstanding	2.630s	127.474us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.070s	246.209us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.070s	246.209us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.070s	246.209us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.070s	246.209us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.580s	110.265us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.650s	1.651ms	1	1	100.00
		kmac_tl_intg_err	3.010s	60.963us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.010s	60.963us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.250s	33.908us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.360s	4.183ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.164m	2.559ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.070s	246.209us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.650s	1.651ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.650s	1.651ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.650s	1.651ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.360s	4.183ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.250s	33.908us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.650s	1.651ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.978m	10.431ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.360s	4.183ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.537m	4.755ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.30570625574943411121069626315087883330853772304218319187325661960715227535532
      Line 178, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4755288329 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4755288329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---