ebd55f1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 59.000s | 6.421ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 7.000s | 15.717us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 24.144us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 284.892us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 12.699us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.027us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 24.144us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 12.699us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 41.000s | 14.795ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 19.000s | 310.315us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.150m | 1.704ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 9.000s | 14.588us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 8.000s | 2.819us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 8.000s | 2.819us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 7.000s | 15.717us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 24.144us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.699us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 13.357us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 7.000s | 15.717us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 24.144us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.699us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 13.357us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 9.000s | 26.050us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 8.000s | 31.620us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.99340742202504623236653934931471939762726650065655888623150270409635107547845
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 2819183 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf191de9f a_data = 0x3368858 a_mask = 0x3 a_size = 0x3 a_param = 0x0 a_source = 0x8f a_opcode = Get a_user = 0x26cfd d_data = 0xca50d5b8 d_size = 0x2 d_param = 0x0 d_source = 0x2e d_opcode = AccessAckData d_error = 0 d_user = 1110101100001 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2819183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.69560919102954480066078041899239066308172258639105515245680675286990648830719
Line 92, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 31619727 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xd24b394c a_data = 0xd273e8bc a_mask = 0x3 a_size = 0x2 a_param = 0x0 a_source = 0x22 a_opcode = PutPartialData a_user = 0x243a7 d_data = 0xc45f5912 d_size = 0x3 d_param = 0x0 d_source = 0xc2 d_opcode = AccessAck d_error = 0 d_user = 1101110000111 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 31619727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.71086051430228856620020789582656147649455738317798900436853750194017151006027
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1027155 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x4ba91864 a_data = 0x431831ce a_mask = 0x0 a_size = 0x2 a_param = 0x0 a_source = 0x3b a_opcode = Invalid, value: 2 a_user = 0x27fa1 d_data = 0x70bf7fa2 d_size = 0x2 d_param = 0x0 d_source = 0xae d_opcode = AccessAck d_error = 0 d_user = 11010111110111 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1027155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---