OTBN Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: `ebd55f1`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	146.696us	1	1	100.00
V1	single_binary	otbn_single	9.000s	52.215us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	22.135us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	24.690us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	190.277us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	17.742us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	56.210us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	24.690us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.742us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	180.694us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	128.917us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	38.000s	124.773us	1	1	100.00
V2	multi_error	otbn_multi_err	36.000s	337.774us	1	1	100.00
V2	back_to_back	otbn_multi	51.000s	191.134us	1	1	100.00
V2	stress_all	otbn_stress_all	41.000s	660.221us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	64.582us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	90.610us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	39.000s	176.543us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	41.142us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	67.788us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	192.928us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	192.928us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	22.135us	1	1	100.00
		otbn_csr_rw	6.000s	24.690us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.742us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	17.881us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	22.135us	1	1	100.00
		otbn_csr_rw	6.000s	24.690us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.742us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	17.881us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	12.000s	35.715us	1	1	100.00
		otbn_dmem_err	9.000s	35.644us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	70.222us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	40.834us	1	1	100.00
		otbn_mac_bignum_acc_err	8.000s	26.651us	1	1	100.00
		otbn_urnd_err	8.000s	25.338us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	10.020us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	27.459us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	48.177us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	11.000s	505.887us	0	1	0.00
		otbn_tl_intg_err	28.000s	177.882us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	15.000s	131.046us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	146.696us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	35.644us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	35.715us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	177.882us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	64.582us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	35.715us	1	1	100.00
		otbn_dmem_err	9.000s	35.644us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	90.610us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.020us	1	1	100.00
		otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	35.715us	1	1	100.00
		otbn_dmem_err	9.000s	35.644us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	90.610us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.020us	1	1	100.00
		otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	64.582us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	35.715us	1	1	100.00
		otbn_dmem_err	9.000s	35.644us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	90.610us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.020us	1	1	100.00
		otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	61.510us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	87.034us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	22.000s	59.676us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	22.000s	59.676us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	24.861us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	1.111ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	70.883us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	70.883us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	10.236us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	51.000s	191.134us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	79.163us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	52.215us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.000s	505.887us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.500m	1.092ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.30726514256896411567914752281008898231158995064676578364128900214170227592087
    Line 166, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1091686515 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1091686515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.32400598972260570108420117685108305045821978813015935735663165281442093677849
Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 505886534 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 505886534 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 505886534 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 505886534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---