ROM_CTRL/32KB Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.220s 580.634us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.860s 300.601us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.870s 371.138us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.630s 130.583us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.230s 128.520us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.120s 178.816us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.870s 371.138us 1 1 100.00
rom_ctrl_csr_aliasing 4.230s 128.520us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.470s 540.631us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.270s 123.907us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.110s 136.851us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.450s 2.071ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.520s 219.454us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.270s 165.370us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.960s 155.653us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.960s 155.653us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.860s 300.601us 1 1 100.00
rom_ctrl_csr_rw 3.870s 371.138us 1 1 100.00
rom_ctrl_csr_aliasing 4.230s 128.520us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.480s 137.140us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.860s 300.601us 1 1 100.00
rom_ctrl_csr_rw 3.870s 371.138us 1 1 100.00
rom_ctrl_csr_aliasing 4.230s 128.520us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.480s 137.140us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.900s 403.427us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
rom_ctrl_tl_intg_err 23.590s 256.332us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.220s 580.634us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.220s 580.634us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.220s 580.634us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.590s 256.332us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 7.520s 219.454us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.900s 403.427us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.503m 666.102us 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.683m 17.208ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets