ROM_CTRL/64KB Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.440s 398.949us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.520s 379.336us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.550s 1.140ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.130s 571.582us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.950s 1.021ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.380s 208.362us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.550s 1.140ms 1 1 100.00
rom_ctrl_csr_aliasing 8.950s 1.021ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.590s 1.209ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.810s 297.798us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 10.570s 1.035ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 23.630s 3.091ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.070s 562.585us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.820s 788.432us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.750s 1.029ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.750s 1.029ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.520s 379.336us 1 1 100.00
rom_ctrl_csr_rw 5.550s 1.140ms 1 1 100.00
rom_ctrl_csr_aliasing 8.950s 1.021ms 1 1 100.00
rom_ctrl_same_csr_outstanding 9.050s 1.162ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.520s 379.336us 1 1 100.00
rom_ctrl_csr_rw 5.550s 1.140ms 1 1 100.00
rom_ctrl_csr_aliasing 8.950s 1.021ms 1 1 100.00
rom_ctrl_same_csr_outstanding 9.050s 1.162ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.310s 1.076ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
rom_ctrl_tl_intg_err 1.097m 873.257us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.440s 398.949us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.440s 398.949us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.440s 398.949us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.097m 873.257us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 14.070s 562.585us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.310s 1.076ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.615m 482.990us 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.268m 11.561ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets