RV_TIMER Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	37.890s	32.732ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.660s	20.424us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.500s	24.300us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.500s	414.175us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.540s	17.723us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.760s	118.665us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.500s	24.300us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	17.723us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	5.519m	179.268ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.459m	1.000s	0	1	0.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.841m	239.826ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.841m	239.826ms	1	1	100.00
V2	stress	rv_timer_stress_all	13.439m	2.232s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.630s	13.683us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.970s	369.787us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.970s	369.787us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.660s	20.424us	1	1	100.00
		rv_timer_csr_rw	1.500s	24.300us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	17.723us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	90.796us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.660s	20.424us	1	1	100.00
		rv_timer_csr_rw	1.500s	24.300us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	17.723us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	90.796us	1	1	100.00
V2		TOTAL			6	7	85.71
V2S	tl_intg_err	rv_timer_sec_cm	1.840s	179.676us	1	1	100.00
		rv_timer_tl_intg_err	2.170s	456.025us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.170s	456.025us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	7.230s	3.481ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			14	16	87.50

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rv_timer_disabled has 1 failures.

    • 0.rv_timer_disabled.98135136524249943397970636952499378870580554196391840239453636010724748650467
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.79166616958080989110799415270255039507360136152051006686709262519362999573203
      Line 96, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3480942634 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3480942634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---