SPI_DEVICE/1R1W Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.583m	39.000ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.880s	70.098us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.480s	29.594us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.100s	1.456ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.740s	1.367ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.620s	161.196us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.480s	29.594us	1	1	100.00
		spi_device_csr_aliasing	15.740s	1.367ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.600s	10.471us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.520s	108.313us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.760s	22.308us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.640s	23.361us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.600s	1.460us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.620s	17.350us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.620s	17.350us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.870s	13.268ms	1	1	100.00
		spi_device_tpm_sts_read	1.430s	14.542us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	30.320s	20.669ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.640s	181.625us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.160s	5.213ms	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.160s	5.213ms	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.120s	282.928us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.120s	282.928us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.120s	282.928us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.120s	282.928us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.120s	282.928us	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.720s	1.520ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	26.650s	4.102ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	26.650s	4.102ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	26.650s	4.102ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.000s	688.652us	1	1	100.00
		spi_device_read_buffer_direct	6.450s	4.568ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	26.650s	4.102ms	1	1	100.00
		spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.590m	15.236ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.020s	137.552us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.020s	137.552us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.583m	39.000ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	47.450s	24.872ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.799m	22.388ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.760s	22.457us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.740s	48.444us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.840s	280.211us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.840s	280.211us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.880s	70.098us	1	1	100.00
		spi_device_csr_rw	2.480s	29.594us	1	1	100.00
		spi_device_csr_aliasing	15.740s	1.367ms	1	1	100.00
		spi_device_same_csr_outstanding	3.660s	62.362us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.880s	70.098us	1	1	100.00
		spi_device_csr_rw	2.480s	29.594us	1	1	100.00
		spi_device_csr_aliasing	15.740s	1.367ms	1	1	100.00
		spi_device_same_csr_outstanding	3.660s	62.362us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.160s	517.194us	1	1	100.00
		spi_device_tl_intg_err	10.400s	832.523us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.400s	832.523us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	56.860s	28.172ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.28845932226457655431343416292579254066735905013685495206752409401060848237230
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  12194655 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[12])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  12194655 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  12194655 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[908])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.7387001538904745094249178895277108377205533543280600913530397275283689912189
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    748304 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    748304 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    822304 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2ac20 [110000101010110000100000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    822304 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xc2ac20 [110000101010110000100000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])