SRAM_CTRL/MAIN Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.790s	2.909ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.810s	133.162us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.560s	41.758us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.510s	156.726us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.860s	40.555us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.390s	349.431us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.560s	41.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	40.555us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.092m	21.170ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	59.650s	2.471ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.207m	4.037ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.994m	11.525ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.030m	46.409ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.211m	15.212ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	52.110s	43.157ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.128m	2.701ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.000s	1.079ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.975m	90.910ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.700s	761.885us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	43.570s	3.075ms	1	1	100.00
		sram_ctrl_throughput_w_readback	42.270s	1.756ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.785m	6.492ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.210s	736.160us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	37.842m	737.559ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	24.980us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.380s	151.317us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.380s	151.317us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.810s	133.162us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	41.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	40.555us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	60.726us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.810s	133.162us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	41.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	40.555us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	60.726us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	42.170s	29.443ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
		sram_ctrl_tl_intg_err	2.400s	873.161us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	873.161us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.785m	6.492ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.785m	6.492ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.560s	41.758us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.128m	2.701ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.128m	2.701ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.128m	2.701ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	52.110s	43.157ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.050s	4.442ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	42.170s	29.443ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.420s	671.664us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.790s	2.909ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.790s	2.909ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.128m	2.701ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	52.110s	43.157ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.790s	2.909ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.560s	8.368us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	22.710s	9.254ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.21807561909882159109121750948287061706490588096494968700969974192587468965591
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 671663987 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x24) != exp (0x7c)
        UVM_INFO @ 671663987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.24095598026613264484306986824768307427690284692249768445012451346491094250404
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8367986 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8367986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---