SRAM_CTRL/RET Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	22.410s	103.362us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.660s	21.089us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.470s	34.269us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.360s	309.032us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.600s	24.441us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.830s	63.731us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.470s	34.269us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	24.441us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.550s	2.517ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.010s	274.193us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.312m	13.751ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.993m	12.586ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.020s	2.794ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.797m	7.105ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.420s	1.554ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.234m	4.272ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.580s	194.759us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.663m	103.700ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	35.270s	1.084ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	35.180s	265.539us	1	1	100.00
		sram_ctrl_throughput_w_readback	3.370s	238.575us	1	1	100.00
V2	regwen	sram_ctrl_regwen	33.330s	1.038ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.690s	93.594us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.759m	6.770ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	15.308us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.390s	230.223us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.390s	230.223us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.660s	21.089us	1	1	100.00
		sram_ctrl_csr_rw	1.470s	34.269us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	24.441us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.900s	46.308us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.660s	21.089us	1	1	100.00
		sram_ctrl_csr_rw	1.470s	34.269us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	24.441us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.900s	46.308us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.600s	1.551ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
		sram_ctrl_tl_intg_err	2.210s	129.531us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.210s	129.531us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.330s	1.038ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	33.330s	1.038ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.470s	34.269us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.234m	4.272ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.234m	4.272ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.234m	4.272ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.420s	1.554ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.880s	33.087us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.600s	1.551ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.290s	32.231us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	22.410s	103.362us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	22.410s	103.362us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.234m	4.272ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.420s	1.554ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	22.410s	103.362us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	12.742us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.720s	2.934ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.18943007853503484212791782137620068941784907879371739918373265562430419051964
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  33087118 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  33087118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.37447562397458478865135159160517075598866476803836486325241811743076766082447
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12742361 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12742361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---