UART Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.110s	975.888us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.600s	15.614us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.330s	14.229us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	229.991us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.490s	18.288us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	76.797us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.330s	14.229us	1	1	100.00
		uart_csr_aliasing	1.490s	18.288us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.310s	33.106ms	1	1	100.00
V2	parity	uart_smoke	5.110s	975.888us	1	1	100.00
		uart_tx_rx	11.310s	33.106ms	1	1	100.00
V2	parity_error	uart_intr	1.380m	230.042ms	1	1	100.00
		uart_rx_parity_err	8.360s	126.141ms	1	1	100.00
V2	watermark	uart_tx_rx	11.310s	33.106ms	1	1	100.00
		uart_intr	1.380m	230.042ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.800s	70.389ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	18.390s	15.598ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	46.190s	55.091ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.380m	230.042ms	1	1	100.00
V2	rx_break_err	uart_intr	1.380m	230.042ms	1	1	100.00
V2	rx_timeout	uart_intr	1.380m	230.042ms	1	1	100.00
V2	perf	uart_perf	1.468m	4.816ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.170s	5.562ms	1	1	100.00
V2	line_loopback	uart_loopback	3.170s	5.562ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	22.590s	62.066ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.760s	6.307ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.920s	7.714ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.160s	5.149ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	49.190s	163.581ms	1	1	100.00
V2	stress_all	uart_stress_all	1.764m	187.033ms	1	1	100.00
V2	alert_test	uart_alert_test	1.550s	24.881us	1	1	100.00
V2	intr_test	uart_intr_test	1.480s	29.922us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.930s	22.956us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.930s	22.956us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.600s	15.614us	1	1	100.00
		uart_csr_rw	1.330s	14.229us	1	1	100.00
		uart_csr_aliasing	1.490s	18.288us	1	1	100.00
		uart_same_csr_outstanding	1.530s	38.161us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.600s	15.614us	1	1	100.00
		uart_csr_rw	1.330s	14.229us	1	1	100.00
		uart_csr_aliasing	1.490s	18.288us	1	1	100.00
		uart_same_csr_outstanding	1.530s	38.161us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.680s	303.947us	1	1	100.00
		uart_tl_intg_err	1.920s	293.179us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.920s	293.179us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.640s	2.843ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00