CHIP Simulation Results

Tuesday April 22 2025 17:07:25 UTC

GitHub Revision: `ebd55f1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.344m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.344m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.943s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.374m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.365m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.118m	4.993ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.118m	4.993ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.118m	4.993ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.577m		0	1	0.00
		chip_sw_example_manufacturer	2.839m		0	1	0.00
		chip_sw_example_concurrency	4.206m	3.790ms	1	1	100.00
		chip_sw_uart_smoketest_signed	20.073s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.120s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	13.540s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	13.540s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.190s	11.247us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	42.203s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.698m	9.699ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.627m	4.121ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.324m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.313m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.304m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.304m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.390s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.390s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.364m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.308m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.392m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.392m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.199m	3.770ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.670m	3.471ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.109m	13.213ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.998s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.182s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.464m	10.042ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.464m	6.347ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.773m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.773m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.001s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.892s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.892s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	12.298s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.687m	3.696ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.262m	4.541ms	1	1	100.00
		chip_sw_aes_idle	4.127m	5.720ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.840m	4.504ms	1	1	100.00
		chip_sw_kmac_idle	4.354m	5.762ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.180s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.949s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.837s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.888s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.653s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.424s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.709s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.768s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.695s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.644s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.653s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.424s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.709s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.768s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.695s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.609s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.570s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.080s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	51.550s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	56.190s	10.320us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.180s		0	1	0.00
		chip_sw_clkmgr_jitter	4.910m	5.822ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.969m	4.667ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.645s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.080s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	54.120s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.990s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	48.380s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	49.120s	10.160us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.058s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.437s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.590s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.211s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.006m	13.669ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.892s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.058s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.006m	13.669ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	18.111s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.521s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.985s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.464s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.485s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.109m	13.213ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.571m	20.021ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.098m	7.307ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.376m	30.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.093m	5.546ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.729s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.303s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.955s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.376m	30.015ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.873s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.126s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.695s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.103s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.959s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.716s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.303s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.586s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.434m	9.839ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.023s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.209s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.673s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	35.086s		0	1	0.00
		chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.879m	7.143ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.280m	11.206ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.370s		0	1	0.00
		chip_prim_tl_access	18.105m	31.328ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.653s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.424s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.709s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.768s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.695s		0	1	0.00
		chip_rv_dm_lc_disabled	8.464m	10.042ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.843m	4.216ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.570s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.095m	4.870ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.127m	5.720ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.345m	4.436ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.080s	10.340us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.840m	4.504ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.865m	4.668ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.607m	4.411ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	56.190s	10.320us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.879m	7.143ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	42.800s	10.260us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.112m	5.170ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.354m	5.762ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.831s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.831s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.936s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.128m	3.387ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.672s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.879m	7.143ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	51.550s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	16.370s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	16.609s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.262m	4.541ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.262m	4.541ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.262m	4.541ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.385m	5.261ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.280m	11.206ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.280m	11.206ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.584m	5.746ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.180s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.370s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.392m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.385m	5.261ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.879m	7.143ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.584m	5.746ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.371m	5.226ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.385m	5.261ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.879m	7.143ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.584m	5.746ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.371m	5.226ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.541s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.586s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.023s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.209s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.673s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	35.086s		0	1	0.00
		chip_sw_lc_ctrl_transition	32.939s		0	1	0.00
		chip_prim_tl_access	18.105m	31.328ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	18.105m	31.328ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	23.238s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.538s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.437s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.609s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.570s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.080s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	51.550s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	56.190s	10.320us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.180s		0	1	0.00
		chip_sw_clkmgr_jitter	4.910m	5.822ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.121m	5.734ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.121m	5.734ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.526m	3.573ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.924m	5.768ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.871m	3.897ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.670m	4.654ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.474m	5.343ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.696m	4.726ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.371m	5.226ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.571m	20.021ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.571m	20.021ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.538m	3.917ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.859m	5.176ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.604m	4.893ms	1	1	100.00
		chip_sw_csrng_smoketest	3.956m	5.346ms	1	1	100.00
		chip_sw_gpio_smoketest	3.791m	4.394ms	1	1	100.00
		chip_sw_hmac_smoketest	4.635m	4.712ms	1	1	100.00
		chip_sw_kmac_smoketest	3.755m	4.679ms	1	1	100.00
		chip_sw_otbn_smoketest	4.751m	6.307ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.837m	6.021ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.133m	4.869ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.274m	5.120ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.258m	4.435ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.090m	4.776ms	1	1	100.00
		chip_sw_uart_smoketest	3.764m	6.100ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.915s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	20.073s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	42.203s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.820s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.488m	6.536ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.196m	5.281ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.129m	6.087ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.408m	6.035ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.771s		0	1	0.00
		chip_rv_dm_lc_disabled	8.464m	10.042ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	16.001s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.923s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	26.746s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.311s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.771s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	27.717s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	14.896s		0	1	0.00
		rom_volatile_raw_unlock	11.139s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.832s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	23.628s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	28.233s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.673m	4.975ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.673m	4.975ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	13.540s		0	1	0.00
		chip_same_csr_outstanding	9.620s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	13.540s		0	1	0.00
		chip_same_csr_outstanding	9.620s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	47.010s	39.463us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.560s	12.309us	1	1	100.00
		xbar_smoke_large_delays	4.402m	2.352ms	1	1	100.00
		xbar_smoke_slow_rsp	6.009m	2.285ms	1	1	100.00
		xbar_random_zero_delays	1.435m	78.788us	1	1	100.00
		xbar_random_large_delays	24.725m	13.321ms	1	1	100.00
		xbar_random_slow_rsp	14.040m	4.994ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.745m	190.551us	1	1	100.00
		xbar_error_and_unmapped_addr	19.360s	15.707us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.024m	181.147us	1	1	100.00
		xbar_error_and_unmapped_addr	19.360s	15.707us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.840m	470.025us	1	1	100.00
		xbar_access_same_device_slow_rsp	13.454m	4.886ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.364m	240.387us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.280m	512.686us	1	1	100.00
		xbar_stress_all_with_error	3.783m	700.669us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	10.443m	257.240us	1	1	100.00
		xbar_stress_all_with_reset_error	1.746m	80.839us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.496s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.443s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.699s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.877s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.418s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.969s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.457s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.354s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.762s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.259s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.214s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.852s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.410s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	10.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	10.945s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.693s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.309s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.785s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.377s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.626s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.229s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.447s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.201s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.014s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.274s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.307s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.289s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.576s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.063s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.407s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.172s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.115s		0	1	0.00
		rom_e2e_asm_init_dev	11.029s		0	1	0.00
		rom_e2e_asm_init_prod	11.021s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.240s		0	1	0.00
		rom_e2e_asm_init_rma	12.840s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.304s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.831s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.817s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.818s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.509m	3.833ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.005m	4.433ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.616s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.985s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.889s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.731s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.685m	16.031ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.834s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.375m	14.461ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.832s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.862s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.616s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.985s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.889s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.358s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.000s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.239s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	57.512s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.691m	12.717ms	1	1	100.00
		chip_plic_all_irqs_0	8.830m	6.545ms	1	1	100.00
		chip_plic_all_irqs_10	9.417m	7.793ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.986m	5.689ms	1	1	100.00
		chip_sw_dma_abort	3.574m	3.681ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.999s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.856s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.276s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.049s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.474s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.639s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.969s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.747s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.255s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	24.979s		0	1	0.00
		chip_sw_mbx_smoketest	4.296m	5.939ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.15451242790319940030511086748112302936060652195817927691199746541901855935529
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (36910d)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (50a1f1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 75.319s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.41947009373655183111020971449310893141683577241816840619831172479708834994078
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (cf96fb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 153.729s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.19004908785203580931213406292844464207559532431503001920897598118900901799903
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (9ca752)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.076s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.42307270573955703854168106883451042989987571245393659577477436828415841385441
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (1fdd76)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 131.286s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.65596679986671636783827774839282261210941019306911142881139149798522055164243
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (0ae3bd)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 127.621s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.95774764070811663478545985815534280850199627459967928389560315562467122867768
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.6781951550562397174052541673691587837401880939763073221188792638764425414286
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.35880828952606725014487748998861418244340708115958173980112234479100864732257
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.102570069780083316659483538626596657587182915346323626802464127878820741230351
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.94558914849748179514861502466324006114795363578978605177325073602104185785134
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.79386456249529454090810925811348386767206009099916004344134409711373543324129
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.70051536541760812635238303514828472670236778795250309305716854019110364761896
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.59741028153092689519278770605527573574507331434312297210025991760428396293364
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.59018473471642280158403474104800267702645487546260022497170985217223350146997
Line 485, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30014.684170 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30014.684170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.49083542540653776043982855592625536832429933080720592373518379630004720446064
Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20021.019188 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20021.019188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.7001521685840572863798433341240545096834566489766903739824768307489956231888
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.479205 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.479205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.34612111678026683400558617535246334803035782805790410672814099177402602281076
Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7142.960950 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (41816680104729424281454044530570944196712465843418664944204368778778299886223 [0x5c7366f67539657469c1b31ff55b8b69d4b60a6cd242e1411b62e4fdcaf46a8f] vs 99533717029040405039953999936056921980849220587207914844300477082055846993703 [0xdc0e16620c89f4d24bc018e8ae75a6a679b9d2a8921b34d6f586faed6e291f27])
  UVM_INFO @ 7142.960950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.33183905635224785331991997612869830385129796864153868739374706747364006638758
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9838.833624 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (73125064956033904046997210961687339510480365501207273271515141525148573356611 [0xa1ab51ef0b1b10260885ac98f48e939a4421c06e5420d0842cdbcc99620bd243] vs 104541917476670509027664659916921658356261344973643404353168953534743747133281 [0xe720a0e1175ae767e5c4ec001e9d7930a434b1584a454cf704875c9c024a7f61])
  UVM_INFO @ 9838.833624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.73776522427412416555086392893048558586332327069905473812267658002308870422346
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3769.563032 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb3d5e4a1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h0  a_user: 'h2694e  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3769.563032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.14994576144683289283530340710190443857920712237127744923311071432449215746085
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3471.207553 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h865977ab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248d8  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3471.207553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.34795172756099536228714316756767119147931789614138768130714887200147704250518
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4120.798500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4120.798500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.33386707066853478790621304520753416799443805713508282505185851550635159109894
    Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3573.023000 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3573.023000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.69786915532267949952797725182991607893242910720663830552661958644730894602751
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4653.847888 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4653.847888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.76388534305606380544372109492074486131602255156290628712981391339894326714923
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36356) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.57644591316660166589691817988189658429425482327054154006026338939166799811143
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4974.675772 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36356) { a_addr: 'h1465110  a_data: 'h4e3d606f  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'h8e  a_opcode: 'h4  a_user: 'h24f47  d_param: 'h0  d_source: 'h8e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4974.675772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.53260664868011876481408925103618224797761571882006477332240326849540337480836
    Line 404, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13213.013736 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13213.013736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.33957748242414044468512049908995979833581639237996682977644826064650228239181
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.21200648986190069401826591263141036172115623672885224518992395170312789536574
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3681.418632 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3681.418632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```