DMA Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	970.147us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.338ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	763.902us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	90.399us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	113.952us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	4.732ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	570.431us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	58.307us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	113.952us	1	1	100.00
		dma_csr_aliasing	10.000s	570.431us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	49.000s	2.732ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.867m	59.522ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.600m	14.381ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.283m	48.991ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.867m	59.522ms	1	1	100.00
V2	dma_abort	dma_abort	9.000s	712.526us	1	1	100.00
V2	dma_stress_all	dma_stress_all	6.533m	123.543ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	12.588us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	439.741us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	439.741us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	90.399us	1	1	100.00
		dma_csr_rw	4.000s	113.952us	1	1	100.00
		dma_csr_aliasing	10.000s	570.431us	1	1	100.00
		dma_same_csr_outstanding	5.000s	372.755us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	90.399us	1	1	100.00
		dma_csr_rw	4.000s	113.952us	1	1	100.00
		dma_csr_aliasing	10.000s	570.431us	1	1	100.00
		dma_same_csr_outstanding	5.000s	372.755us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	28.000s	210.624us	1	1	100.00
		dma_generic_stress	2.283m	48.991ms	1	1	100.00
		dma_handshake_stress	4.867m	59.522ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	94.625us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.017m	3.541ms	1	1	100.00
		dma_longer_transfer	7.000s	809.153us	1	1	100.00
		TOTAL			21	21	100.00