EDN Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.700s	102.638us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.800s	13.790us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.750s	28.914us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.150s	59.752us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.000s	19.240us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.010s	148.560us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.750s	28.914us	1	1	100.00
		edn_csr_aliasing	2.000s	19.240us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.700s	67.976us	1	1	100.00
V2	csrng_commands	edn_genbits	1.700s	67.976us	1	1	100.00
V2	genbits	edn_genbits	1.700s	67.976us	1	1	100.00
V2	interrupts	edn_intr	1.700s	34.019us	1	1	100.00
V2	alerts	edn_alert	2.120s	401.003us	1	1	100.00
V2	errs	edn_err	1.860s	18.900us	1	1	100.00
V2	disable	edn_disable	1.730s	22.592us	1	1	100.00
		edn_disable_auto_req_mode	2.030s	66.612us	1	1	100.00
V2	stress_all	edn_stress_all	2.350s	247.899us	1	1	100.00
V2	intr_test	edn_intr_test	1.850s	15.746us	1	1	100.00
V2	alert_test	edn_alert_test	1.620s	35.409us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.350s	99.802us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.350s	99.802us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.800s	13.790us	1	1	100.00
		edn_csr_rw	1.750s	28.914us	1	1	100.00
		edn_csr_aliasing	2.000s	19.240us	1	1	100.00
		edn_same_csr_outstanding	2.150s	36.345us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.800s	13.790us	1	1	100.00
		edn_csr_rw	1.750s	28.914us	1	1	100.00
		edn_csr_aliasing	2.000s	19.240us	1	1	100.00
		edn_same_csr_outstanding	2.150s	36.345us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.220s	1.045ms	1	1	100.00
		edn_tl_intg_err	3.660s	167.891us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.700s	106.089us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.120s	401.003us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.220s	1.045ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.220s	1.045ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.220s	1.045ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.220s	1.045ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.120s	401.003us	1	1	100.00
		edn_sec_cm	4.220s	1.045ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.120s	401.003us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.660s	167.891us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	16.180s	2.046ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00