HMAC Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.490s 2.708ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.520s 20.647us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.750s 91.427us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.790s 408.545us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.100s 382.378us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.640s 42.059us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.750s 91.427us 1 1 100.00
hmac_csr_aliasing 5.100s 382.378us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 29.700s 1.613ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.033m 6.177ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.930s 693.077us 1 1 100.00
hmac_test_sha384_vectors 22.920s 527.272us 1 1 100.00
hmac_test_sha512_vectors 7.295m 15.109ms 1 1 100.00
hmac_test_hmac256_vectors 7.500s 421.486us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 325.117us 1 1 100.00
hmac_test_hmac512_vectors 12.470s 344.192us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.840s 1.710ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.359m 5.631ms 1 1 100.00
V2 error hmac_error 1.680s 15.720us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.141m 7.079ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.490s 2.708ms 1 1 100.00
hmac_long_msg 29.700s 1.613ms 1 1 100.00
hmac_back_pressure 1.033m 6.177ms 1 1 100.00
hmac_datapath_stress 1.359m 5.631ms 1 1 100.00
hmac_burst_wr 11.840s 1.710ms 1 1 100.00
hmac_stress_all 8.330s 950.662us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.490s 2.708ms 1 1 100.00
hmac_long_msg 29.700s 1.613ms 1 1 100.00
hmac_back_pressure 1.033m 6.177ms 1 1 100.00
hmac_datapath_stress 1.359m 5.631ms 1 1 100.00
hmac_wipe_secret 1.141m 7.079ms 1 1 100.00
hmac_test_sha256_vectors 9.930s 693.077us 1 1 100.00
hmac_test_sha384_vectors 22.920s 527.272us 1 1 100.00
hmac_test_sha512_vectors 7.295m 15.109ms 1 1 100.00
hmac_test_hmac256_vectors 7.500s 421.486us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 325.117us 1 1 100.00
hmac_test_hmac512_vectors 12.470s 344.192us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.490s 2.708ms 1 1 100.00
hmac_long_msg 29.700s 1.613ms 1 1 100.00
hmac_back_pressure 1.033m 6.177ms 1 1 100.00
hmac_datapath_stress 1.359m 5.631ms 1 1 100.00
hmac_burst_wr 11.840s 1.710ms 1 1 100.00
hmac_error 1.680s 15.720us 1 1 100.00
hmac_wipe_secret 1.141m 7.079ms 1 1 100.00
hmac_test_sha256_vectors 9.930s 693.077us 1 1 100.00
hmac_test_sha384_vectors 22.920s 527.272us 1 1 100.00
hmac_test_sha512_vectors 7.295m 15.109ms 1 1 100.00
hmac_test_hmac256_vectors 7.500s 421.486us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 325.117us 1 1 100.00
hmac_test_hmac512_vectors 12.470s 344.192us 1 1 100.00
hmac_stress_all 8.330s 950.662us 1 1 100.00
V2 stress_all hmac_stress_all 8.330s 950.662us 1 1 100.00
V2 alert_test hmac_alert_test 1.400s 13.449us 1 1 100.00
V2 intr_test hmac_intr_test 1.450s 23.696us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.190s 282.252us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.190s 282.252us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.520s 20.647us 1 1 100.00
hmac_csr_rw 1.750s 91.427us 1 1 100.00
hmac_csr_aliasing 5.100s 382.378us 1 1 100.00
hmac_same_csr_outstanding 2.130s 92.831us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.520s 20.647us 1 1 100.00
hmac_csr_rw 1.750s 91.427us 1 1 100.00
hmac_csr_aliasing 5.100s 382.378us 1 1 100.00
hmac_same_csr_outstanding 2.130s 92.831us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.010s 73.632us 1 1 100.00
hmac_tl_intg_err 2.630s 84.723us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.630s 84.723us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.490s 2.708ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.230s 781.601us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.432m 21.930ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.620s 802.196us 1 1 100.00
TOTAL 28 28 100.00