I2C Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	53.450s	8.445ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	27.720s	2.306ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	48.132us	1	1	100.00
V1	csr_rw	i2c_csr_rw	2.000s	56.899us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.300s	353.397us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.880s	147.576us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.880s	42.362us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.000s	56.899us	1	1	100.00
		i2c_csr_aliasing	2.880s	147.576us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.170s	146.583us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	10.961m	18.762ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	6.390s	544.618us	1	1	100.00
V2	host_override	i2c_host_override	1.570s	42.934us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.901m	7.356ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	35.440s	3.881ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.800s	133.166us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.130s	259.369us	1	1	100.00
		i2c_host_fifo_reset_rx	3.780s	298.170us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.274m	3.764ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	24.300s	1.636ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.270s	162.822us	1	1	100.00
V2	target_glitch	i2c_target_glitch	8.130s	8.628ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	7.099m	74.823ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	6.000s	1.606ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	37.750s	4.881ms	1	1	100.00
		i2c_target_intr_smoke	4.200s	746.631us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.940s	1.233ms	1	1	100.00
		i2c_target_fifo_reset_tx	2.380s	472.168us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	46.940s	24.526ms	1	1	100.00
		i2c_target_stress_rd	37.750s	4.881ms	1	1	100.00
		i2c_target_intr_stress_wr	8.960s	4.114ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	7.640s	2.778ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.859m	3.304ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.810s	1.188ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.760s	359.827us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.130s	386.096us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.180s	505.266us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	6.390s	544.618us	1	1	100.00
		i2c_host_perf_precise	2.660s	100.839us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	24.300s	1.636ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.240s	76.003us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.000s	1.555ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.550s	534.310us	1	1	100.00
		i2c_target_nack_txstretch	1.940s	255.938us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.640s	3.133ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.880s	482.172us	1	1	100.00
V2	alert_test	i2c_alert_test	1.480s	49.372us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	20.752us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.300s	72.851us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.300s	72.851us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	48.132us	1	1	100.00
		i2c_csr_rw	2.000s	56.899us	1	1	100.00
		i2c_csr_aliasing	2.880s	147.576us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	61.403us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	48.132us	1	1	100.00
		i2c_csr_rw	2.000s	56.899us	1	1	100.00
		i2c_csr_aliasing	2.880s	147.576us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	61.403us	1	1	100.00
V2		TOTAL			38	38	100.00
V2S	tl_intg_err	i2c_tl_intg_err	2.530s	85.979us	1	1	100.00
		i2c_sec_cm	1.800s	131.060us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.530s	85.979us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.480s	2.060ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.120s	285.830us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.250s	1.480ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			47	50	94.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.20913306635898093306645382667746042556288862664787355850558364005827191853956
      Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2059882057 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2059882057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.55911705385321294284741706168287663871864625814991603401381680142193046051824
      Line 106, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1480088813 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1480088813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.44360821394005206451750943612390990220424329505722950266579365182135707570117
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 285829676 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 231 [0xe7])
        UVM_INFO @ 285829676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---