KEYMGR Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	12.950s	6.819ms	1	1	100.00
V1	random	keymgr_random	2.510s	29.225us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.840s	132.749us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.670s	172.089us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.280s	2.117ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.750s	507.382us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.050s	86.291us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.670s	172.089us	1	1	100.00
		keymgr_csr_aliasing	5.750s	507.382us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.630s	27.739us	1	1	100.00
V2	sideload	keymgr_sideload	3.610s	162.601us	1	1	100.00
		keymgr_sideload_kmac	3.280s	66.882us	1	1	100.00
		keymgr_sideload_aes	2.680s	48.162us	1	1	100.00
		keymgr_sideload_otbn	3.840s	142.907us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.450s	27.113us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.550s	75.448us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.540s	1.276ms	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.580s	113.444us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.250s	1.052ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.260s	56.045us	1	1	100.00
V2	stress_all	keymgr_stress_all	3.838m	16.420ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.800s	13.061us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.660s	13.534us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.210s	21.401us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.210s	21.401us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.840s	132.749us	1	1	100.00
		keymgr_csr_rw	1.670s	172.089us	1	1	100.00
		keymgr_csr_aliasing	5.750s	507.382us	1	1	100.00
		keymgr_same_csr_outstanding	1.820s	20.408us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.840s	132.749us	1	1	100.00
		keymgr_csr_rw	1.670s	172.089us	1	1	100.00
		keymgr_csr_aliasing	5.750s	507.382us	1	1	100.00
		keymgr_same_csr_outstanding	1.820s	20.408us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
		keymgr_tl_intg_err	1.940s	65.743us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.630s	128.456us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.630s	128.456us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.630s	128.456us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.630s	128.456us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.930s	485.894us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.940s	65.743us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.630s	128.456us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.630s	27.739us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.510s	29.225us	1	1	100.00
		keymgr_csr_rw	1.670s	172.089us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.510s	29.225us	1	1	100.00
		keymgr_csr_rw	1.670s	172.089us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.510s	29.225us	1	1	100.00
		keymgr_csr_rw	1.670s	172.089us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.550s	75.448us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.250s	1.052ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.250s	1.052ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.510s	29.225us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.780s	128.520us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	6.900s	196.923us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.550s	75.448us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	6.900s	196.923us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	6.900s	196.923us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	6.900s	196.923us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.060s	1.218ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	6.900s	196.923us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.000s	274.374us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.74363003926681310437560041406286561500417553805674406470535820123233586579674
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @  65742897 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @  65742897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---