KMAC/MASKED Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.370s	633.448us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.980s	47.217us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.900s	20.037us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.810s	509.489us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.400s	496.626us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.110s	70.776us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.900s	20.037us	1	1	100.00
		kmac_csr_aliasing	7.400s	496.626us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.570s	23.066us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.830s	58.443us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.827m	369.326ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.856m	23.632ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.700s	27.319ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.600s	9.839ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.024m	14.342ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.014m	37.786ms	1	1	100.00
		kmac_test_vectors_shake_128	28.136m	131.442ms	1	1	100.00
		kmac_test_vectors_shake_256	32.512m	303.543ms	1	1	100.00
		kmac_test_vectors_kmac	3.100s	37.294us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.460s	188.042us	1	1	100.00
V2	sideload	kmac_sideload	5.221m	55.016ms	1	1	100.00
V2	app	kmac_app	4.755m	13.194ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.726m	3.028ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.186m	29.710ms	1	1	100.00
V2	error	kmac_error	2.393m	30.221ms	1	1	100.00
V2	key_error	kmac_key_error	9.090s	1.227ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.990s	60.812us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	4.000s	205.730us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.200s	34.061us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	21.480s	9.048ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.970s	45.349us	1	1	100.00
V2	stress_all	kmac_stress_all	12.274m	92.798ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	41.634us	1	1	100.00
V2	alert_test	kmac_alert_test	2.160s	18.633us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.880s	82.603us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.880s	82.603us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.980s	47.217us	1	1	100.00
		kmac_csr_rw	1.900s	20.037us	1	1	100.00
		kmac_csr_aliasing	7.400s	496.626us	1	1	100.00
		kmac_same_csr_outstanding	2.920s	467.180us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.980s	47.217us	1	1	100.00
		kmac_csr_rw	1.900s	20.037us	1	1	100.00
		kmac_csr_aliasing	7.400s	496.626us	1	1	100.00
		kmac_same_csr_outstanding	2.920s	467.180us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.950s	62.276us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.950s	62.276us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.950s	62.276us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.950s	62.276us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.220s	327.224us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	43.730s	3.832ms	1	1	100.00
		kmac_tl_intg_err	1.760s	34.024us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.760s	34.024us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.970s	45.349us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.370s	633.448us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.221m	55.016ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.950s	62.276us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.730s	3.832ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.730s	3.832ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.730s	3.832ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.370s	633.448us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.970s	45.349us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.730s	3.832ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.477m	20.568ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.370s	633.448us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	14.850s	1.529ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.70880565030502760433322067903195591885284864435280893972754841023409464470579
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @ 327223545 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @ 327223545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.45393562654236848007682660018013177541824188341295267697470876597863020054199
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  34024111 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  34024111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.51920480391257615315431204057988279756822604908847595001221760848514391728236
      Line 105, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1528602932 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1528602932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---