KMAC/UNMASKED Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.320s	1.838ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	310.569us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.920s	103.620us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.660s	974.937us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.080s	241.111us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.120s	43.379us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.920s	103.620us	1	1	100.00
		kmac_csr_aliasing	4.080s	241.111us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.920s	15.244us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	37.888us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	29.232m	277.022ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.583m	59.367ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.225m	133.533ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.692m	20.448ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.966m	265.764ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.570s	531.272us	1	1	100.00
		kmac_test_vectors_shake_128	2.765m	54.859ms	1	1	100.00
		kmac_test_vectors_shake_256	17.913m	34.155ms	1	1	100.00
		kmac_test_vectors_kmac	3.520s	104.962us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.600s	757.552us	1	1	100.00
V2	sideload	kmac_sideload	2.370m	24.209ms	1	1	100.00
V2	app	kmac_app	36.370s	2.200ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.554m	20.143ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.485m	28.074ms	1	1	100.00
V2	error	kmac_error	3.557m	14.922ms	1	1	100.00
V2	key_error	kmac_key_error	4.400s	853.621us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.280s	228.116us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.080s	10.207ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.630s	1.499ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	22.710s	13.661ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.380s	39.429us	1	1	100.00
V2	stress_all	kmac_stress_all	7.900m	83.231ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.660s	20.001us	1	1	100.00
V2	alert_test	kmac_alert_test	1.820s	136.253us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.920s	176.042us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.920s	176.042us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	310.569us	1	1	100.00
		kmac_csr_rw	1.920s	103.620us	1	1	100.00
		kmac_csr_aliasing	4.080s	241.111us	1	1	100.00
		kmac_same_csr_outstanding	2.680s	1.027ms	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	310.569us	1	1	100.00
		kmac_csr_rw	1.920s	103.620us	1	1	100.00
		kmac_csr_aliasing	4.080s	241.111us	1	1	100.00
		kmac_same_csr_outstanding	2.680s	1.027ms	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	213.882us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	213.882us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	213.882us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	213.882us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.760s	90.595us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	18.960s	1.662ms	1	1	100.00
		kmac_tl_intg_err	1.720s	39.998us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.720s	39.998us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.380s	39.429us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.320s	1.838ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.370m	24.209ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	213.882us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	18.960s	1.662ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	18.960s	1.662ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	18.960s	1.662ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.320s	1.838ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.380s	39.429us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	18.960s	1.662ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.936m	19.236ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.320s	1.838ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.281m	41.967ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.53341107365290487746469782047760968065316317114165875234591711891347871296756
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  39997789 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  39997789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---