856cba6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 32.000s | 752.246us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 37.795us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 15.468us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 166.956us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 19.829us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.197us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 15.468us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 19.829us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 35.000s | 12.621ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.533m | 7.957ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 32.000s | 9.759ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 17.215us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 984.113ns | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 984.113ns | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 37.795us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 15.468us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 19.829us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 17.390us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 37.795us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 15.468us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 19.829us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 17.390us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 39.512us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 18.278us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.43469218870630314476275444302945412183796608607719286725620664568233101339956
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 984113 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x3c9f60f5 a_data = 0x9e2a20fd a_mask = 0x2 a_size = 0x0 a_param = 0x0 a_source = 0xc0 a_opcode = Invalid, value: 2 a_user = 0x25a57 d_data = 0x9cf6aad6 d_size = 0x2 d_param = 0x0 d_source = 0xc8 d_opcode = AccessAckData d_error = 0 d_user = 10101010100001 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 984113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.52485492359444097750899232656578871700614106641223215497770399113341044997887
Line 96, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 18277753 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x325fd4fc a_data = 0x609fa3ad a_mask = 0x1 a_size = 0x0 a_param = 0x0 a_source = 0x93 a_opcode = Get a_user = 0x2702b d_data = 0x2dc56ae3 d_size = 0x1 d_param = 0x0 d_source = 0xa d_opcode = AccessAckData d_error = 0 d_user = 11101110111010 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 18277753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.77752212587425965406672205003150048055094746619323377418949405185234100989172
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1197267 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x8667b593 a_data = 0x8fc735de a_mask = 0x0 a_size = 0x0 a_param = 0x0 a_source = 0xc6 a_opcode = Invalid, value: 5 a_user = 0x26ce7 d_data = 0xe871abe3 d_size = 0x3 d_param = 0x0 d_source = 0xa2 d_opcode = AccessAck d_error = 0 d_user = 1000101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1197267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---