OTBN Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	561.767us	1	1	100.00
V1	single_binary	otbn_single	10.000s	28.686us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	37.330us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	14.554us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	194.454us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	30.097us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	154.487us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	14.554us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.097us	1	1	100.00
V1	mem_walk	otbn_mem_walk	19.000s	561.706us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	6.283ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	22.000s	93.830us	1	1	100.00
V2	multi_error	otbn_multi_err	48.000s	290.010us	1	1	100.00
V2	back_to_back	otbn_multi	1.167m	1.675ms	1	1	100.00
V2	stress_all	otbn_stress_all	15.000s	120.168us	1	1	100.00
V2	lc_escalation	otbn_escalate	13.000s	34.855us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	16.909us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	38.916us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	54.909us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	29.907us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	188.237us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	188.237us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	37.330us	1	1	100.00
		otbn_csr_rw	6.000s	14.554us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.097us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	65.944us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	37.330us	1	1	100.00
		otbn_csr_rw	6.000s	14.554us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.097us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	65.944us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	158.056us	1	1	100.00
		otbn_dmem_err	10.000s	35.756us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	56.000s	248.783us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	18.329us	1	1	100.00
		otbn_mac_bignum_acc_err	13.000s	42.723us	1	1	100.00
		otbn_urnd_err	6.000s	29.189us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	21.389us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	40.052us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	116.511us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	17.000s	77.216us	0	1	0.00
		otbn_tl_intg_err	20.000s	1.321ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	25.000s	197.756us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	561.767us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	35.756us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	158.056us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	1.321ms	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	13.000s	34.855us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	158.056us	1	1	100.00
		otbn_dmem_err	10.000s	35.756us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	16.909us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	21.389us	1	1	100.00
		otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	158.056us	1	1	100.00
		otbn_dmem_err	10.000s	35.756us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	16.909us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	21.389us	1	1	100.00
		otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	13.000s	34.855us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	158.056us	1	1	100.00
		otbn_dmem_err	10.000s	35.756us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	16.909us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	21.389us	1	1	100.00
		otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	24.759us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	20.891us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	21.000s	60.034us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	21.000s	60.034us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	31.279us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	68.932us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	45.223us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	45.223us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	18.554us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.167m	1.675ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	27.950us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	28.686us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	17.000s	77.216us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.700m	1.072ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.21135814133616314457489646311693201931660888397645566660567609138092511299762
      Line 163, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1071959991 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1071959991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.115002765450386983110987134045026160408020952635456468846438488664638181476166
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18554050 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  18554050 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  18554050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.94084564812169533896807380532268298971570175906311499269182387578972343292614
      Line 120, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 77216274 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 77216274 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  77216274 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  77216274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---