ROM_CTRL/64KB Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.200s 581.705us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.620s 385.338us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.970s 284.658us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.460s 216.640us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.700s 701.491us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.310s 238.781us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.970s 284.658us 1 1 100.00
rom_ctrl_csr_aliasing 5.700s 701.491us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.780s 1.027ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.170s 291.396us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.620s 224.439us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 21.900s 849.496us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.940s 3.342ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.540s 2.777ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.070s 208.600us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.070s 208.600us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.620s 385.338us 1 1 100.00
rom_ctrl_csr_rw 5.970s 284.658us 1 1 100.00
rom_ctrl_csr_aliasing 5.700s 701.491us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.560s 1.025ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.620s 385.338us 1 1 100.00
rom_ctrl_csr_rw 5.970s 284.658us 1 1 100.00
rom_ctrl_csr_aliasing 5.700s 701.491us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.560s 1.025ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.400s 3.406ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
rom_ctrl_tl_intg_err 1.151m 2.152ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.200s 581.705us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.200s 581.705us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.200s 581.705us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.151m 2.152ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 12.940s 3.342ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.400s 3.406ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.231m 1.846ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 22.810s 11.158ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets