RV_TIMER Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.994m	195.107ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.750s	14.730us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.400s	12.618us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.640s	257.433us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.800s	15.222us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.040s	114.213us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.400s	12.618us	1	1	100.00
		rv_timer_csr_aliasing	1.800s	15.222us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.773m	45.020ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.187m	260.411ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.733m	284.772ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.733m	284.772ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.393m	638.523ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.420s	28.952us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.190s	54.073us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.190s	54.073us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.750s	14.730us	1	1	100.00
		rv_timer_csr_rw	1.400s	12.618us	1	1	100.00
		rv_timer_csr_aliasing	1.800s	15.222us	1	1	100.00
		rv_timer_same_csr_outstanding	1.910s	40.230us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.750s	14.730us	1	1	100.00
		rv_timer_csr_rw	1.400s	12.618us	1	1	100.00
		rv_timer_csr_aliasing	1.800s	15.222us	1	1	100.00
		rv_timer_same_csr_outstanding	1.910s	40.230us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.790s	435.773us	1	1	100.00
		rv_timer_tl_intg_err	1.750s	108.423us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.750s	108.423us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	7.300s	4.519ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00