SPI_DEVICE/1R1W Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.128m	44.481ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.030s	71.341us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.310s	249.740us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.710s	183.225us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.400s	914.944us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.390s	25.732us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.310s	249.740us	1	1	100.00
		spi_device_csr_aliasing	18.400s	914.944us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.520s	23.763us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.360s	57.019us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.660s	31.512us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	1.436us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.770s	1.475us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.770s	38.776us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.770s	38.776us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	11.150s	20.695ms	1	1	100.00
		spi_device_tpm_sts_read	1.760s	86.344us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.190s	34.588ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.010s	7.498ms	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.520s	4.264ms	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.520s	4.264ms	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.170s	93.387us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.170s	93.387us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.170s	93.387us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.170s	93.387us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.170s	93.387us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.800s	124.846us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.560s	120.673us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.560s	120.673us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.560s	120.673us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.730s	98.039us	1	1	100.00
		spi_device_read_buffer_direct	4.040s	173.860us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.560s	120.673us	1	1	100.00
		spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	49.070s	10.336ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.230s	283.415us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.230s	283.415us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.128m	44.481ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.540s	575.388us	1	1	100.00
V2	stress_all	spi_device_stress_all	4.194m	216.327ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.570s	23.535us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.720s	15.106us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.920s	214.502us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.920s	214.502us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.030s	71.341us	1	1	100.00
		spi_device_csr_rw	2.310s	249.740us	1	1	100.00
		spi_device_csr_aliasing	18.400s	914.944us	1	1	100.00
		spi_device_same_csr_outstanding	3.120s	47.159us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.030s	71.341us	1	1	100.00
		spi_device_csr_rw	2.310s	249.740us	1	1	100.00
		spi_device_csr_aliasing	18.400s	914.944us	1	1	100.00
		spi_device_same_csr_outstanding	3.120s	47.159us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.110s	183.084us	1	1	100.00
		spi_device_tl_intg_err	16.130s	2.352ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.130s	2.352ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.464m	264.359ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.83716643882957723673047371424463282717281629516058743814696499506684231931583
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    946189 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[77])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    946189 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    946189 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[973])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.34134693570724201317203300156228156203899997991454573635788959164268475662001
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    811816 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    811816 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    874816 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x33b672 [1100111011011001110010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    874816 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x33b672 [1100111011011001110010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])